高速序列匯流排系統之驗證環境

Abstract

隨著硬體設計愈來愈複雜, 以及晶片下線成本愈來愈昂貴, 驗證的重要性不可同日而語。使用觀察波形的方法來尋找設計中的錯誤是相當耗費人力資源的, 而且與迅速推出市場的目標相違背。 本論文描述一些驗證技巧，包含transaction-based, assertion-based, simulation-based, coverage-based 等等的方法來建構一個驗證環境, 用以確定此設計是否符合工程師們的期望與規格書的規定。此外, 我們使用Verilog程式語言以及驗證語言的擴增工具, 來模擬出功能性匯流排的行為以及連線監視器，不但可以讓待測的硬體與我們的驗證環境整合上更容易, 撰寫測試程式也將更迅速。 PCI Express是一個高速串流匯流排協定, 已漸漸成為工作站或個人電腦的企業新趨勢, 將以其高速, 點對點的特性取代舊式的共享平行匯流排。在新的2.0規格中, 連線速度倍增, 挑戰性也增加, 我將會建構一個針對PCI Express 2.0的驗證環境, 根據相當高的測試涵蓋率, 來讓硬體工程師與驗證工程師對他們的設計更具信心。

As the complexity of IC designs and price to tape-out increase, verification has become a vital step in the design flow. Debugging in a large and complicated system by waveform is both time and human resource consuming. Therefore, the time to market will increase. This thesis introduces several verification skills, which includes transactionbased, assertion-based, simulation-based and coverage-based methods. These skills not only can be used to develop a verification environment, but also confirm the design is fit in with designer's hope and the requirement of specification. Furthermore, we use Verilog with Verification Language Extension (VLE) toolkits to model bus functional model (or so-called transaction verification model) and link monitor which make Design Under Test (DUT) integration easier and test case development more quickly. PCI Express is a high-speed serial bus protocol and becomes an industry trend on work stations or personal computers. This high-speed point-topoint serial bus will soon replace current legacy shared parallel buses. In [2], the speed per lane/second/side is doubled and has more challenges. The goal of this thesis is to create a test environment which is aimed at PCI Express 2.0 platform. According to the experimental results, the functional coverage is very high. Design engineers and verification engineers can have more confidence in their design after verifying their design using this verification tool.