用於通訊系統CMOS寬頻放大器之設計與研製

Abstract

本論文介紹CMOS寬頻低雜訊放大器的設計與研製。該低雜訊放大器可被使用於各種不同的通訊系統。本論文描述三種不同類型的低雜訊放大器。全部的低雜訊放大器都是以0.18微米CMOS科技所製作。 第一個低雜訊放大器為了節省大量的晶片面積，因此設計時沒有使用任何電感。該放大器使用了雜訊抵消的技術，以達到低雜訊指標。測量結果顯示了小訊號增益14.3 dB以及45 MHz至3.1 GHz的頻寬。在500 MHz至2 GHz的雜訊指標為3.15至3.68 dB。 第二個設計是一個應用於3.1至5 GHz超寬頻架構的低雜訊放大器。該放大器使用了一個堆疊式放大級以及回授的方式。放大器的負載則是一個包含電感，電容以及電阻的特殊網路。測量出的小訊號增益為7.7dB，而頻寬則是2.8至4.5 GHz. 本論文最後介紹的低雜訊放大器，乃為3.1至10.6 GHz超寬頻系統所設計。主要的放大級是包含回授電阻的正反器。為了增進電路表現，在特定的訊號路徑上使用了數個電感。模擬結果顯示了小訊號增益10 dB，而頻寬是 0.4至10.7 GHz。在3.1至10.6 GHz超寬頻的頻帶內，實現了5.5至6.5 dB的平坦雜訊指標。

The thesis introduces the design and implementation of CMOS wide-band low-noise amplifiers (LNAs). These LNAs may be used for various communication systems. Three different types of LNAs are described in this thesis. All of the LNAs are fabricated in 0.18 μm CMOS technology. The first LNA is designed without any inductor for decreasing a large amount of chip area. It uses noise-canceling technique for low noise figure (NF). Measured small-signal gain is 14.3 dB with bandwidth of 45 MHz to 3.1 GHz. NF is 3.15 to 3.68 dB in 500 MHz to 2 GHz. The second design is a LNA for 3.1-5 GHz ultra-wideband applications. It uses a casode stage with feedback topology. The load of this amplifier is a special network with inductors, capacitors and a resistor. Measured small-signal gain is 7.7 dB, and bandwidth is 2.8-4.5 GHz. The last LNA introduced in the thesis is designed for 3.1-10.6 GHz ultra-wideband systems. Main amplifying stages are inverters with feedback resistors. Several inductors are used in certain signal paths to improve circuit performance. Simulation results shows small-signal gain of 10 dB with bandwidth of 0.4-10.7 GHz. Flat NF of 5.5-6.5 dB is achieved in 3.1-10.6 GHz ultra-wideband frequency band.