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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33567完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥(Sy-Yen Kuo) | |
| dc.contributor.author | Chih-Wei Ling | en |
| dc.contributor.author | 凌志瑋 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:47:46Z | - |
| dc.date.available | 2006-07-25 | |
| dc.date.copyright | 2006-07-25 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-17 | |
| dc.identifier.citation | [1] Andrea Bevilacqua and Ali M. Niknejad, “An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, pp. 2259-2268, Dec. 2004.
[2] Aly Ismail and Asad A. Abidi, “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, pp. 2269-2277, Dec. 2004. [3] N. Shiramizu, T. Masuda, M. Tanabe, and K. Washio, “A 3-10 GHz bandwidth low-noise and low-power amplifier for full-band UWB communications in 0.25-μm SiGe BiCMOS technology,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 39-42, June 2005. [4] P. Heydari and D. Lin, “A performance optimized CMOS distributed LNA for UWB receivers,” IEEE Custom Integrated Circuits Conference, pp. 337-340, Sept. 2005. [5] Y. Park, C.-H. Lee, J.D. Cressler, J. Laskar, and A. Joseph, “A very low power SiGe LNA for UWB application,” IEEE Mircowave Symposium Digest, pp. 1041-1044 , June 2005. [6] Chang-Wan Kim, Min-Suk Kang, and Phan Tuan Anh, Hoon-Tae Kim, and Sang-Gug Lee, “An ultra-wideband CMOS low noise amplifier for 3–5-GHz UWB system,” IEEE J. Solid-State Circuits, vol. 40, pp. 544-547, Feb. 2005. [7] Hiroyuki Satou, Hiroshi Yamazaki, Kazuhiko Kobayashi, Toshihiko Mori, and Yuu Watanabe, “5.3GHz 1.6dB NF CMOS low noise amplifier using 0.11μm technology,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 109-112, June 2004. [8] Behnam Mohammadi and C. Andre T. Salama, “A 5.8 GHz CMOS LNA for WPAN applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 113-116, June 2004. [9] Trung-Kien Nguyen, Nam-lin Oh, Hyung-Chul Choi, Kuk-Ju Ihm, and Sang-Gug Lee “A 5.2 GHz image rejection CMOS low noise amplifier for WLAN applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 197-200, June 2004. [10] Sachio Iida1, Katsuyuki Tanaka, and Hideyuki Suzuki, Naoto Yoshikawa, Norio Shoji, Bernie Griffiths, Derek Mellor, Frank Hayden, Iain Butler, and Jeremy Chatwin, “A 3.1 to 5GHz CMOS DSSS UWB transceiver for WPANs,” IEEE Solid-State Circuit Conference, pp. 214-215, pp. 594, Feb. 2005. [11] R. Salerno, M. Tiebout, H. Paule, M. Streibl, C.Sandner, and K. Kropf, “ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB,” IEEE Solid-State Circuit Conference, ESSCIRC, pp. 219-222, Sept. 2005. [12] A. Bevilacqua, C. Sandner, A. Gerosa, and A. Neviani, “A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers,” IEEE Mircowave and Wireless Components Letters , vol. 16, pp. 134-136, Mar. 2006. [13] Federico Bruccoleri, Eric A. M. Klumperink, and Bram Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. Solid-State Circuits, vol. 39, pp. 275-282, Feb. 2004. [14] S.B.T. Wang, A.M. Niknejad, and R.W. Brodersen, “A sub-mW 960-MHz ultra-wideband CMOS LNA,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 35-38, June 2005. [15] G. Gramegna, M. Paparo, P.G. Erratico, and P. De Vita, “A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA,” IEEE J. Solid-State Circuits, vol. 36, pp. 1010-1017, July 2001. [16] A.A. Moneim Youssef, K. Sharaf, H.F. Ragaie, and M. Marzouk Ibrahim, “VLSI design of CMOS image-reject LNA for 950-MHz wireless receivers,” IEEE International Conference on Circuits and Systems for Communications, pp. 330-333, June 2002. [17] P. Leroux, J. Janssens, and M. Steyaert, “A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz,” IEEE J. Solid-State Circuits, vol. 37, pp. 760-765, June 2002. [18] F. Gatta, E. Sacchi, F. Svelto, P. Vilmercati, and R. Castello, “A 2-dB noise figure 900-MHz differential CMOS LNA,” IEEE J. Solid-State Circuits, vol. 36, pp. 1444-1452, Oct. 2001. [19] Xiaomin Yang, T. Wu, and J. McMacken, “Design of LNA at 2.4 GHz using 0.25 μm technology,” Silicon Monolithic Integrated Circuits in RF Systems, pp. 12-17, Sept. 2001. [20] B.A. Floyd and D. Ozis,, “Low-noise amplifier comparison at 2 GHz in 0.25-μm and 0.18-μm RF-CMOS and SiGe BiCMOS,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 185-188, June 2004. [21] Sherif Galal and Behzad Razavi, “10Gb/s limiting amplifier and laser/modulator driver in 0.18μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 38, pp. 2138-2146, Dec. 2003. [22] Behzad Razavi, “Prospects of CMOS technology for high-speed optical communication circuits,” IEEE J. Solid-State Circuits, vol. 37, pp. 1135-1145, Sept. 2002. [23] IEEE 802.15 WPAN High Rate Alternative PHY Task Group 3a (2003), http://www.ieee802.org/15/pub/TG3a.html [24] S. Shekhar, X. Li and D.J. Allstot, “A CMOS 3.1-10.6GHz UWB LNA employing stagger-compensated series peaking,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2006. [25] Chang-Tsung Fu and Chien-Nan Kuo, “3~11-GHz CMOS UWB LNA using dual feedback for broadband matching,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33567 | - |
| dc.description.abstract | 本論文介紹CMOS寬頻低雜訊放大器的設計與研製。該低雜訊放大器可被使用於各種不同的通訊系統。本論文描述三種不同類型的低雜訊放大器。全部的低雜訊放大器都是以0.18微米CMOS科技所製作。
第一個低雜訊放大器為了節省大量的晶片面積，因此設計時沒有使用任何電感。該放大器使用了雜訊抵消的技術，以達到低雜訊指標。測量結果顯示了小訊號增益14.3 dB以及45 MHz至3.1 GHz的頻寬。在500 MHz至2 GHz的雜訊指標為3.15至3.68 dB。 第二個設計是一個應用於3.1至5 GHz超寬頻架構的低雜訊放大器。該放大器使用了一個堆疊式放大級以及回授的方式。放大器的負載則是一個包含電感，電容以及電阻的特殊網路。測量出的小訊號增益為7.7dB，而頻寬則是2.8至4.5 GHz. 本論文最後介紹的低雜訊放大器，乃為3.1至10.6 GHz超寬頻系統所設計。主要的放大級是包含回授電阻的正反器。為了增進電路表現，在特定的訊號路徑上使用了數個電感。模擬結果顯示了小訊號增益10 dB，而頻寬是 0.4至10.7 GHz。在3.1至10.6 GHz超寬頻的頻帶內，實現了5.5至6.5 dB的平坦雜訊指標。 | zh_TW |
| dc.description.abstract | The thesis introduces the design and implementation of CMOS wide-band low-noise amplifiers (LNAs). These LNAs may be used for various communication systems. Three different types of LNAs are described in this thesis. All of the LNAs are fabricated in 0.18 μm CMOS technology.
The first LNA is designed without any inductor for decreasing a large amount of chip area. It uses noise-canceling technique for low noise figure (NF). Measured small-signal gain is 14.3 dB with bandwidth of 45 MHz to 3.1 GHz. NF is 3.15 to 3.68 dB in 500 MHz to 2 GHz. The second design is a LNA for 3.1-5 GHz ultra-wideband applications. It uses a casode stage with feedback topology. The load of this amplifier is a special network with inductors, capacitors and a resistor. Measured small-signal gain is 7.7 dB, and bandwidth is 2.8-4.5 GHz. The last LNA introduced in the thesis is designed for 3.1-10.6 GHz ultra-wideband systems. Main amplifying stages are inverters with feedback resistors. Several inductors are used in certain signal paths to improve circuit performance. Simulation results shows small-signal gain of 10 dB with bandwidth of 0.4-10.7 GHz. Flat NF of 5.5-6.5 dB is achieved in 3.1-10.6 GHz ultra-wideband frequency band. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:47:46Z (GMT). No. of bitstreams: 1 ntu-95-R91943023-1.pdf: 2703218 bytes, checksum: f3d0324692b4384723f800ae5aad1d6d (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | CHAPTER 1 INTRODUCTION…………………………………………….1
1.1 Motivation………………………………………………………...1 1.2 Published Results…………………………………………………2 1.3 Outline of Thesis………………………………………………….5 CHAPTER 2 A CMOS LOW NOISE AMPLIFIER FOR VERY LOW FREQUENCY TO 3 GHZ APPLICATIONS……………………8 2.1 Introduction……………………………………………………....8 2.2 Noise Canceling Technique……………………………………....9 2.3 Circuit Design…………………………………………………...11 2.4 Simulation and Measurement Results………………………....14 CHAPTER 3 A CMOS LOW NOISE AMPLIFIER FOR 3.1-5 GHZ ULTRA- WIDEBAND APPLICATIONS……………………………….25 3.1 System Overview of Ultra-Wideband………………………….25 3.2 Design Technique………………………………………………..26 3.2.1 LRC Load of the Amplifier………………………………..26 3.2.2 Feedback Technique and Cascode Stage………………….28 3.2.3 Input and Output Impedance Matching………………….32 3.3 Simulation and Measurement Results…………………………32 CHAPTER 4 A CMOS LOW NOISE AMPLIFIER FOR 3.1 ~ 10.6 GHZ ULTRA-WIDEBAND SYSTEMS…………………………….41 4.1 Introduction……………………………………………………41 4.2 Circuit Implementation……………………………………….42 4.2.1 Inverters with Feedback Technique……………………..42 4.2.2 Feedback Inductors……………………………………….44 4.2.3 Input and Output Matching Network…………………...44 4.3 Simulation Results……………………………………………..49 CHAPTER 5 CONCLUSION…………………………………………….55 REFERENCES……………………………………………………………57 | |
| dc.language.iso | en | |
| dc.subject | 放大器 | zh_TW |
| dc.subject | 寬頻 | zh_TW |
| dc.subject | 低雜訊放大器 | zh_TW |
| dc.subject | LNA | en |
| dc.subject | wide-band | en |
| dc.subject | amplifiers | en |
| dc.title | 用於通訊系統CMOS寬頻放大器之設計與研製 | zh_TW |
| dc.title | Design and Implementation of CMOS Wide-band Amplifiers for Communication Systems | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 王暉(Huei Wang) | |
| dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),張鴻埜(Hong-Yeh Chang) | |
| dc.subject.keyword | 寬頻,放大器,低雜訊放大器, | zh_TW |
| dc.subject.keyword | wide-band,amplifiers,LNA, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-95-1.pdf 未授權公開取用 | 2.64 MB | Adobe PDF |
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