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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32924| Title: | 20-GHz時脈倍頻單元設計與分析以0.18-um CMOS製程製作 Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-um CMOS Technology |
| Authors: | Sheng-Hann Wu 吳昇翰 |
| Advisor: | 李致毅(Jri Lee) |
| Keyword: | 鎖相迴路,時脈倍頻單元, CMU,PLL,OC-768, |
| Publication Year : | 2006 |
| Degree: | 碩士 |
| Abstract: | 在這裡提出以0.18-um CMOS製程所製作20-GHz時脈倍頻單元, 應用於OC-768系統上, 採用雙迴路及三階濾波器以消除Jitter的影響. 所設計之電路達到輸出Jitter 0.2ps,rms及 4.5ps,pp同時在1.8V的偏壓下消耗40mW. A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32924 |
| Fulltext Rights: | 有償授權 |
| Appears in Collections: | 電子工程學研究所 |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-95-1.pdf Restricted Access | 3.27 MB | Adobe PDF |
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