以解析模型為主運用Mathcad估算VRM之半導體切換功率損耗

Abstract

隨著微處理器和晶片組的快速進步，使得電壓調節模組（Voltage Regulator Modules，VRM）設計開發，面臨相當大的挑戰，必須思考如何達成小體積高效率的技術，其中提高切換頻率是明顯的技術趨勢，因此，Power MOSFET切換功率損耗的比重會提高，所以，預測電路功率損耗的工作，將是設計開發的重要工作。 理論分析方面，先介紹三種功率損耗分析模型技術，其中的解析模型特性，很適合電路開發階段的大量資料處理，並且為符合高切換頻率的趨勢，必須考慮寄生元件的變化影響，因此，使用由Y. Ren等人所提出與實際驗證之Power MOSFET損耗解析模型，來當成理論架構背景，本論文的主旨：將此精確的Power MOSFET功率損耗解析模型，轉成實用之分析與設計的工具。 在模擬驗證方面，利用Mathcad數學模擬軟體，將大量的數學方程式與MOSFET參數電腦化，再以實際的同步整流降壓電路為例，說明模擬工具的使用流程步驟，並分析寄生電感對功率損耗分佈的影響。 最後，總結本論文的成果，並說明未來的工作方向。

Power efficiency is one of the most critical considerations in the voltage regulator modules (VRM) for computer central processor applications. These losses are becoming even more significant now as the tendency of the switching frequency is getting higher. This is the focus of thesis. Among the various loss components, it is generally true that the switching power losses associated with the various power semiconductor device are most difficult to estimate accurately. The thesis starts with a review of several means to estimate the losses and concludes with the choice of the analytical differential equation-based model first reported by Y. Ren etc. This method is a compromise of accuracy and user friendliness. An example of a practical VRM buck converter was used to illustrate the procedures for estimating the losses and converter efficiency. The equations and the procedure were computerized in a Mathcad program for the ease of the users. Nonlinear parasitic capacitor effects of power MOSFETs, temperature effects of conduction voltage drops were taken into considerations. All the parameters of the semiconductor devices can be obtained from manufactors' datasheet. The parasitic inductances of the devices and the printed circuit board are also taken into consideration. This program should be helpful in evaluating the power losses and the voltage rating of the power semiconductor devices.