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標題: | 整合型錯誤更正碼之演算法及積體電路架構設計 Algorithm and VLSI Architecture of Unified FEC Decoder Designs |
作者: | Fan-Min Li 李芳明 |
指導教授: | 吳安宇 |
關鍵字: | 前向錯誤更正碼,渦輪碼,迴旋碼,疊代運算,提早終止, forward error correction,FEC,Turbo code,Convolutional code,iterative decoding,early termination,ET, |
出版年 : | 2007 |
學位: | 博士 |
摘要: | 在先進的前向錯誤更正碼(Forward Error Correction, FEC)標準裏,同時採用了迴旋碼和渦輪碼的編碼方法,所以我們需要一個可重置的錯誤更正解碼設計。此外,渦輪解碼是藉由疊代運算完成,為了降低它所造成的電源消耗和時間延遲,我們需要一個可以依據通訊環境的好壞,而提早終止(Early Termination, ET)疊代運算的機制。在本論文中,我們提出了一個整合型錯誤更正解碼器,針對了可動態運算和可重置的兩個特點而設計。
在之前的文獻裡,有很多關於疊代運算終止方法的研究,然而大部份的討論專注在可完成的解碼(假設接收端的資訊,已足夠在解碼過程中,分辨出傳送端的資訊)。在本論文中,藉由外部資訊轉移曲線(Extrinsic Information Transform, EXIT)圖,我們討論了解碼能力的極限。我們之後提出了一個資訊測量的方法,使用信號的相關性來預測解碼的極限值。另外,在解碼極限值的輔助下,我們提出了兩個疊代運算提早停止的方法(ET-I和ET-II)。當通道環境很好訊雜比高的時候,傳送的資訊很早就已解出,所以疊代運算可以提早停止(可完成的解碼);另一方面,當通道環境很壞訊雜比低的時候,干擾已超出解碼器的能力極限,所以疊代運算亦可以提早停止(無法完成的解碼)。電腦模擬顯示,ET-I方法幾乎不會影響位元錯誤率,而ET-II方法亦能滿足系統規定。 在可重置的設計裡,我們首先有系統的分析Viterbi演算法和MAP演算法的時序圖。接著我們介紹可以在時序圖作變化的三種技巧︰「分散」、「指標」、和「平行」。另外我們提出以基本運算單元作為基礎,分析時序圖的關鍵特性。經由時序的分析,我們發展了VA/MAP時序圖。藉著互補Viterbi和MAP解碼程序裡閒置的部份,使得VA/MAP時序圖具有三種運作模式(「VA模式」、「MAP模式」、和「共同VA/MAP模式」)。接著在硬體設計方面,我們建立了FEC運算核心。針對四種不同的應用狀況,使用著可以把FEC運算核心搭配適當的記憶體,完成一個完整的FEC解碼器(「單模式迴旋解碼器」、「單模式渦輪解碼器」、「雙模式迴旋渦輪解碼器」、和「三模式迴旋渦輪解碼器」)。最後,我們在台積電的0.18μm製程,驗證了3GPP應用的FEC運算核心硬體設計原型。 To satisfy the advanced Forward-Error-Correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a reconfigurable FEC decoder is needed. Moreover, to reduce the power and latency of the iterative Turbo decoding, an Early Termination (ET) mechanism, in which the FEC decoder can stop according to the channel environment, is needed. In this literature, we propose a unified FEC decoder that contains the features of the dynamic computation and reconfigurable function. Although many stopping methods of iterative decoding have been discussed in the literatures extensively, many of them only focus on the solvable decoding (information is enough for successful decoding). In this literature, we discuss the limitation of the decoding ability based on the extrinsic information transform (EXIT) chart. Then, we propose a new information measurement by using cross correlation to predict the decoding threshold. Moreover, we propose two early termination (ET) schemes (ET-I and ET-II) based on the predicted decoding threshold. The iterative decoding can stop in either high-SNR situations where the decoded bits are highly reliable (solvable decoding), or low-SNR situations where the decoder already has no capability to decode (unsolvable decoding). The simulation results show that the reduced iterations due to the ET-I scheme almost will not affect the BER performance, and the ones due to the ET-II scheme can still satisfy the requirement of the specification. For the reconfigurable design, we first systematically analyze the timing charts of both the Viterbi algorithm and the MAP algorithm. Then, three techniques, including Distribution, Pointer, and Parallel schemes, are introduced. Furthermore, we propose a tile-based methodology to analyze the key features of timing charts. On the basis of the timing analysis, we develop a VA/MAP timing chart that has three modes (VA mode, MAP mode, and concurrent VA/MAP mode) by complementing the idle time of both Viterbi and MAP decoding procedures. Then, we construct a triple-mode FEC kernel. By integrating the FEC kernel with different size of memory, we can construct a types of FEC decoders for different application scenarios, such as 1) stand-alone Convolutional decoder (VA mode), 2) stand-alone Turbo decoder (MAP mode), 3) dual-mode Convolutional/Turbo decoder (VA mode and MAP mode), and 4) triple-mode Convolutional/Turbo decoder (VA mode, MAP mode, and concurrent VA/MAP mode). Finally, a prototyping FEC kernel processor that is compliant to 3GPP standard is verified in TSMC 0.18-μm CMOS process. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30627 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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