考慮多重邊界與模式時序限制下利用正規化解決緩衝器置入及尺寸設計問題

Abstract

隨著製程科技進入超微米時代，互連延遲在電路中占了的極大的比例，而緩衝器置入技術是減少互連延遲最有效的技術之一。然而，當現有的緩衝器置入技術考慮製程邊界與不同操作模式的時序限制時，所有可能的緩衝器置入解決方案數量在運算的過程中將成指數成長。 在本篇論文中，我們提出一個三階段的緩衝器置入和尺寸設計技術，此技術利用正規化引擎的優點，同時也滿足多重邊界與模式的時序限制。實驗結果顯示，我們提出的技術在一個合理的運行時間中，平均可以減少關鍵路徑中 62.14％ 的緩衝器面積。

Interconnect delay in the routed circuit becomes dominant as process technology goes into deep submicron range. Buffer insertion is one of the most effective techniques to reduce the interconnect delay. However, when multiple operation modes and process corners are taken into consideration, the number of possible solutions of existing works grows exponentially. In this work, we present a 3-phase buffer insertion and sizing technique taking the advantage of formal engine while the multi-corner multi-mode (MCMM) timing constraints are satisfied at the same time. The experimental results show that our approach can achieve 62.14% buffer area reduction on the most critical path on average within a reasonable runtime.