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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30140完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang (Ric) | |
| dc.contributor.author | Man-Yu Li | en |
| dc.contributor.author | 李曼鈺 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:38:57Z | - |
| dc.date.available | 2012-10-20 | |
| dc.date.copyright | 2011-10-20 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-02 | |
| dc.identifier.citation | [1] L.P.P.P. van Ginneken, “Buffer placement in distributed RC-tree networks for minimal Elmore delay,” International Symposium on Circuits and Systems, pp.865-868, 1990.
[2] C. N. Sze, C. J. Alpert, J. Hu, and W. Shi, “Path-based buffer insertion,” Design Automation Conference, pp.509-514, 2005. [3] J. Lillis, C. K. Cheng, and T. -T. Y. Lin, “Optimal wire sizing and buffer insertion for low power and a generalized delay model,” IEEE Journal of Solid State Circuits, vol.31, no.3, pp.437-447, Mar. 1996. [4] Chris C. N. Chu and D. F. Wong, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23, no.1, pp.136-141, Jan. 2004. [5] Z. Li and W. Shi, “An O(bn2) time algorithm for optimal buffer insertion with b buffer types,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.484-489, 2006. [6] I. -M. Liu, A. Aziz, D. F. Wong, and H. Zhou, “An efficient buffer insertion algorithm for large networks based on Lagrangian relaxation,” International Conference on Computer Design, pp.210-215, 1999. [7] H. R. Kheirabadi, M. S. Zamani, and M. Saeedi, “An efficient analytical approach to path-based buffer insertion,” IEEE Computer Science Annual Symposium on VLSI, pp.219-224, 2007. [8] W. Shi, Z. Li, and C. J. Alpert, “Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost,” Asia and South Pacific Design Automation Conference, pp.609-614, 2004. [9] V. Khandelwal, A. Davoodi, A. Nanavati, and A. Srivastava, “A probabilistic approach to buffer insertion,” International Conference on Computer-Aided Design, pp.560-567, 2003. [10] L. Deng and M. D. F. Wong, “Buffer insertion under process variations for delay minimization,” International Conference on Computer-Aided Design, pp.317-321, 2005. [11] J. Xiong, K. H. Tam, and L. He, “Buffer insertion considering process varitaion,” Design, Automation and Test in Europe, pp.970-975, 2005. [12] J. Xiong and L. He, “Fast buffer insertion considering process variations,” International Symposium on Physical Design, pp.128-135, 2006. [13] R. Chen and H. Zhou, “Fast min-cost buffer insertion under process variations,” Design Automation Conference, pp.1-6, 2007. [14] R. Chen and H. Zhou, “Fast buffer insertion for yield optimization under process variations,” Asia and South Pacific Design Automation Conference, pp.19-24, 2007. [15] V. Mahalingam and N. Ranganathan, “A fuzzy approach for variation aware buffer insertion and driver sizing,” IEEE Computer Society Annual Symposium on VLSI, pp.329-334, 2008. [16] W. C. Elmore, “The transient analysis of damped linear networks with particular regard to wideband amplifiers,” Journal of Applied Physics, vol.19, pp.55-63, Jan. 1948. [17] A. Mutlu and M. Rahman, “Statistical methods for the estimation of process variation effects on circuit operation,” IEEE Transactions on Electronics Packaging Manufacturing, vol.28, no.4, pp.364-375, Oct. 2005. [18] D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, “Statistical timing analysis: from basic principles to state of the art,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.4, pp.589-607, Apr. 2008. [19] L. Xie, A. Davoodi, J. Zhang, and T. H. Wu, “Adjustment-based modeling for statistical static timing analysis with high dimension of variability,” International Conference on Computer-Aided Design, pp.181-184, 2008. [20] S. Onaissi and F. N. Najm, “A linear-time approach for static timing analysis covering all process corners,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.7, pp.1291-1304, July 2008. [21] I. Keller, K. H. Tam, and V. Kariat, “Challenges in gate level modeling for delay and SI at 65nm and below,” Design Automation Conference, pp.468-473, July 2008. [22] L. G. Silva, M. Silveira, and J. R. Phillips, “Efficient computation of the worst-delay corner,” Design Automation & Test in Europe, pp.1-6, 2007. [23] J. -J. Nien, S. -H. Tsai, and C. -Y. Huang, “A unified multi-corner multi-mode static timing analysis engine,” Asia and South Pacific Design Automation Conference, pp.669-674, 2010. [24] N. Een and N. Sorenson, “Translating pseudo-Boolean constraints into SAT,” Journal of Satisfiability, Boolean Modeling and Computation, pp.1-26, 2006. [25] N. Een and N. Sorensson. MiniSat. [Online]. http://minisat.se/MiniSat.htm | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30140 | - |
| dc.description.abstract | 隨著製程科技進入超微米時代，互連延遲在電路中占了的極大的比例，而緩衝器置入技術是減少互連延遲最有效的技術之一。然而，當現有的緩衝器置入技術考慮製程邊界與不同操作模式的時序限制時，所有可能的緩衝器置入解決方案數量在運算的過程中將成指數成長。
在本篇論文中，我們提出一個三階段的緩衝器置入和尺寸設計技術，此技術利用正規化引擎的優點，同時也滿足多重邊界與模式的時序限制。實驗結果顯示，我們提出的技術在一個合理的運行時間中，平均可以減少關鍵路徑中 62.14％ 的緩衝器面積。 | zh_TW |
| dc.description.abstract | Interconnect delay in the routed circuit becomes dominant as process technology goes into deep submicron range. Buffer insertion is one of the most effective techniques to reduce the interconnect delay. However, when multiple operation modes and process corners are taken into consideration, the number of possible solutions of existing works grows exponentially.
In this work, we present a 3-phase buffer insertion and sizing technique taking the advantage of formal engine while the multi-corner multi-mode (MCMM) timing constraints are satisfied at the same time. The experimental results show that our approach can achieve 62.14% buffer area reduction on the most critical path on average within a reasonable runtime. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:38:57Z (GMT). No. of bitstreams: 1 ntu-100-R98921052-1.pdf: 959037 bytes, checksum: 9608745d33a13b4614e160b936baa0af (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii ABSTRACT iii TABLE OF CONTENTS iv LIST OF FIGURES vii LIST OF TABLES ix Chapter 1 Introduction 1 Chapter 2 Preliminaries 4 2.1 Delay Model 4 2.1.1 Delay Model under Single Mode 4 2.1.2 Delay Model under MCMM 5 2.2 Static Timing Analysis 6 2.2.1 Static Timing Analysis 6 2.2.2 MCMM STA 8 2.3 Van Ginneken’s Dynamic Programming 10 2.4 Path-Based Buffer Insertion 12 2.5 Formal-Assisted Buffer Insertion 13 2.6 Buffer Sizing 14 Chapter 3 Problem Description 16 3.1 Buffer Insertion and Sizing under MCMM 16 3.1.1 VGDP Extension 16 3.1.2 PBBI Extension 17 3.2 Problem Definition 17 Chapter 4 Formal-Assisted Buffer Insertion and Sizing 19 4.1 FBIS Overview 19 4.2 Boolean Variables in FBIS 21 4.3 FBIS Technique 21 4.3.1 Buffer Removal Phase 23 4.3.2 Buffer Size-Down Phase 24 4.3.3 Buffer Size-Up Phase 26 4.4 Buffer Placement Restriction 27 Chapter 5 Implementation 30 5.1 Program Flow 30 5.2 Library 30 5.2.1 Cell Library 30 5.2.2 Buffer Library 31 5.3 Data Structure 32 5.4 Formal Engine 34 Chapter 6 Experimental Results 35 6.1 Analysis on Buffer Cost Reduction 36 6.1.1 FBIS on VGDP Extension 36 6.1.2 FBIS on PBBI Extension 38 6.2 Runtime Comparison with Other Works 39 6.3 Analysis on RAT Constraints 41 Chapter 7 Conclusions and Future Works 44 REFERENCE 45 | |
| dc.language.iso | en | |
| dc.subject | 緩衝器置入 | zh_TW |
| dc.subject | 多重操作模式 | zh_TW |
| dc.subject | 緩衝器尺寸設計 | zh_TW |
| dc.subject | 正規化 | zh_TW |
| dc.subject | 多重邊界 | zh_TW |
| dc.subject | buffer insertion | en |
| dc.subject | multi-corner | en |
| dc.subject | multi-mode | en |
| dc.subject | formal | en |
| dc.subject | buffer sizing | en |
| dc.title | 考慮多重邊界與模式時序限制下利用正規化解決緩衝器置入及尺寸設計問題 | zh_TW |
| dc.title | A Formal-Assisted Buffer Insertion and Gate Sizing Technique Considering Multi-Corner Multi-Mode Timing Constraints | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張耀文(Yao-Wen Chang),李毅郎(Yih-Lang Li) | |
| dc.subject.keyword | 緩衝器置入,緩衝器尺寸設計,正規化,多重操作模式,多重邊界, | zh_TW |
| dc.subject.keyword | buffer insertion,buffer sizing,formal,multi-mode,multi-corner, | en |
| dc.relation.page | 48 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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