JPEG-LS編碼器之交易層級模型及其驗證使用SystemC

Abstract

系統單晶片 (System on Chip，SoC) 設計隨著半導體製程的進步，其設計愈來愈複雜，系統設計者面臨更大的系統設計與硬體驗證的諸多挑戰。因此開始尋求可以處理複雜系統，並且能夠盡快將產品導入市場的方法。為了簡化晶片設計的流程，系統層級設計因此變的更加重要。 SystemC 2.0 提供交易層級模型 (Transaction Level Modeling) 一個方便的設計方式，讓設計者以更高階的視野來看待整個系統的設計，在設計的初期即可進行系統的驗證，避免系統設計到RTL (Register Transfer Level) 時才發現錯誤，減少設計的成本。 本論文以SystemC 2.0為基礎，呈現JPEG-LS交易層級模型的設計流程，從高階的演算法層級一直演進到RTL，在不同的模型之間說明設計的差異並進行驗證及效能的分析。

With the ever-increasing complexity of System-on-Chip, the designer faces great challenges to design a system. So the designer has been searching for new methodology that can handle the complexity with increased productivity and decreased time-to-market. In order to simplify the design flow of an application specific integrated circuit, the system level design issue is getting more important. SystemC provides a convenient design flow for transaction level modeling and allow the designers create the design of the whole system on a high level stage, and verify the system at the early model, as well as down to the RTL model. Consequently, it can reduce the design cost. In this thesis we present the design flow of transaction level modeling of a JPEG-LS encoder based on SystemC from the algorithm level down to the register transfer level, and compare the diversity of different models. Finally, we verify the system design and performance analysis.