一個低功率且快速鎖定的數位延遲鎖相迴路

Abstract

在傳統的連續逼近式延遲鎖相迴路中，由於響應時間的關係，鎖定時間仍然大大地增加，為了改善鎖定速度，本論文提出一個數位延遲鎖相迴路，可以達到低功率且快速鎖定的特性。本晶片使用台積電0.13-μm 1P8M CMOS 製程製作，晶片面積為0.77 x 0.79mm2，核心面積為0.226 x 0.076mm2，操作頻率範圍從50MHz到200MHz，在最高操作頻率下，量測到的功率消耗為0.259mW，鎖定時間為4個時脈週期，當操作頻率為200MHz的時候，量測到的方均根抖動和峰值抖動分別是3.67ps和34.17ps。

In conventional SARDLL, the lock time still increases seriously because of the response time. A digital DLL is proposed in this work to improve the locking speed. The proposed DLL can exhibit features of low-power and fast-lock. This work is fabricated in TSMC 0.13-μm 1P8M CMOS technology. The chip area is 0.77 x 0.79mm2, and the active area is 0.226 x 0.076mm2. The proposed DLL can operate in the range from 50MHz to 200MHz. The measured power consumption is 0.259mW at the maximum operation frequency 200MHz. The lock time is 4 clock cycles. When the operation frequency is 200MHz, the measured rms jitter and peak-to-peak jitter is 3.67ps and 34.17ps, respectively.