省電式晶片網路設計共同合成演算法之分析

Abstract

在微米製程上，晶片網路的概念已經被提出來解決晶片系統上的溝通問題。一個完整的晶片網路設計需考量到軟體和硬體兩方面的架構。硬體的架構包括了多種不同型態之處理元件的選擇和硬體架構的排列方式。軟體的設計上需要考量每個程序要在哪個處理元件上面執行和執行的順序以及程序間的溝通。對一個目標程式而言，為了找到最佳的硬體設計，需要同時考量軟體和硬體兩方面。先前相關的成果已經提出了一些共同合成演算法，他們的設計目標是針對嵌入式系統上面的應用程式，在符合時間需求的狀況下讓能源消耗越小越好。在這篇論文中，我們將以下幾種不同形態演算法所跑出來的解和跑出解的時間。所比較的演算法包含了發展分支定界演算法、疊代演算法和四種以模擬冶鐵為基礎的演算法。

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of SoC (System-on-Chip) design in deep submicron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of PEs (Processing Elements) with multiple types and their topology. The software architecture contains the allocation of tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have proposed some co-synthesis algorithms, which minimizes energy consumption while meeting the real-time requirements commonly seen in the embedded applications. In this thesis, we compare the solution quality and running time of several types of co-synthesis algorithms including branch and bound algorithm, iteraitve algorithm and SA-based algorithm.