應用於60-GHz無線通訊系統之外差式接收機

Abstract

我們提出一個採用兩次降頻的外差式接收機，它可減緩振盪器及除頻器的速度需求。此接收機包含低雜訊放大器，射頻混波器，中頻放大器，兩組中頻混波器和正交相位除頻器。此正交相位除頻器可產生正交相位之本地端振盪訊號，使接收訊號達成正交分離的效果。此外差式接收機採用九十奈米互補式金氧半場效電晶體製程製作，其操作在54.7至58.3 GHz時，可達到7.3至9.1 dB之雜訊指數和21.8至24.8 dB之電壓轉換增益。射頻訊號經由接收機降頻後之正交訊號，其增益誤差小於1.6 dB，角度誤差小於1.1度。此接收機電路在1.5 V電壓操作下消耗75 mW

A heterodyne receiver performs frequency down conversion in two steps to relax oscillator and divider speed requirements. This receiver incorporates a low noise amplifier, a RF mixer, a IF amplifier, two sets of IF mixers and a injection-locked quadrature frequency divider to generate LO signals for I/Q separation. Fabricated in 90-nm digital CMOS technology, the receiver achieves a noise figure of 7.3 to 9.1 dB from 54.7 to 58.3 GHz with a conversion gain of 21.8 to 24.8 dB and I/Q mismatch of 1.6dB/1.1 degrees. The circuit consumes 75 mW from a 1.5-V supply.