數位電路邏輯元件模型及時序分析

Abstract

在近代的IC設計中功耗是重要的課題，也是設計的瓶頸所在。隨著製程的進步，漏電流所造成的的功耗儼然取代動態轉換功耗變成最重要的電能消耗，複合臨界電壓電路設計就是一種設計方式用來有效減少電路的漏電流來達到減少功耗的目的，加入睡眠電晶體就是其中一種有效的方式，利用高臨界電壓的電晶體來限制低臨界電壓電晶體電路在休眠狀態下的漏電流，但這方式將會對現有的靜態時序分析產生衝擊。本篇論文的重點並不放在如何有效解決時序分析方面的問題，而是建立一個簡單且準確的電流源模型以及完整的模擬方案，使能夠取代原本的元件來做整個電路的模擬，有效模擬出有加入睡眠電晶體狀態下的時間與狀態。

Recent research has shown that the increasing leakage power is becoming a critical issue in the design of low power portable IC. To cope with the problem of leakage power, MTCMOS technology such as implementation of a sleep transistor has been proven effect in power reduction. However the existing Static Timing Analysis methods have not focused on this issue. This thesis presents a methodology for synthesizing a new Current Source Model from Spice models. Then with the newly synthesized Current Source Model, a complete procedure for the timing analysis of a circuit with inserted sleep transistor will be presented. In addition this procedure can be extended to account for the effect of IR drop during STA.