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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26980完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
| dc.contributor.author | Jen-Wei Kuo | en |
| dc.contributor.author | 郭人瑋 | zh_TW |
| dc.date.accessioned | 2021-06-12T17:53:13Z | - |
| dc.date.available | 2008-04-01 | |
| dc.date.copyright | 2008-04-01 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-03-25 | |
| dc.identifier.citation | [1] S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, pp. 23–29, July–Aug, 1999.
[2] D. Duarte, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir, “Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks,” in Procs. of VLSI Design, pp. 248–253, 2001. [3] G. Moore, “No exponential is forever: But forever can be delayed,” in IEEE ISSCC Dig. Tech. Papers, pp. 20–23, 2003 [4] J. Kao, S. Narendra, and A. Chandrakasan, “Subthreshold Leakage modeling and reduction techniques,” in Proc. of ICCAD, pp. 141–149, 2002 [5] L. Wei et al., “Design and optimization of dual-threshold circuits for low-voltage low-power applications,” IEEE Trans. on VLSI Systems, pp. 16–24, 1999 [6] S. Sirichotiyakul et al., “Stand-by Power Minimization through Simulataneous Threshold Voltage Selection and Circuit Sizing,” in Proc. of the 36th DAC, pp. 436–441, 1999. [7] S.Mutah et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,” IEEE JSSC, pp. 847–853, 1995. [8] M. Anis, S. Areibi, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proc. of DAC, pp. 480–485, 2002 [9] V. Khandelwal, and A. Srivastava; “Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors ,” in Proc. Of ICCAD, pp. 533–536, 2004 [10] J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns,” in Proc. of DAC, pp. 495–500, 1998 [11] B. H. Calhoun, F. A. Honoré, and A. P. Chandrakasan, “A Leakage Reduction Methodology for Distributed MTCMOS,” IEEE JSSC Vol.39, No. 5, pp. 818–826, May 2004 [12] Open Source ECSM Format Specification Version 1.2 September2005. http://www.cadence.com/webforms/ecsm. [13] Composite Current Source (CCS) Modeling Technology Version 1.0 http://www.synopsys.com/cgi-bin/tapin. [14] K. Chopra, C. Kashyap, H. Su, and D. Blaauw, “Current Source Driver Model Synthesis and Worst-case Alignment for Accurate Timing and Noise Analysis,” IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Vol. 11, No. 2, pp. 157-166, April 2003 [15] Mohab Anis, Shawki Areibi, Mohamed Mahmoud, and Mohamed Elmasry, 'Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique,' dac, p. 480, 39th Design Automation Conference (DAC'02), 2002 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/26980 | - |
| dc.description.abstract | 在近代的IC設計中功耗是重要的課題，也是設計的瓶頸所在。隨著製程的進步，漏電流所造成的的功耗儼然取代動態轉換功耗變成最重要的電能消耗，複合臨界電壓電路設計就是一種設計方式用來有效減少電路的漏電流來達到減少功耗的目的，加入睡眠電晶體就是其中一種有效的方式，利用高臨界電壓的電晶體來限制低臨界電壓電晶體電路在休眠狀態下的漏電流，但這方式將會對現有的靜態時序分析產生衝擊。本篇論文的重點並不放在如何有效解決時序分析方面的問題，而是建立一個簡單且準確的電流源模型以及完整的模擬方案，使能夠取代原本的元件來做整個電路的模擬，有效模擬出有加入睡眠電晶體狀態下的時間與狀態。 | zh_TW |
| dc.description.abstract | Recent research has shown that the increasing leakage power is becoming a critical issue in the design of low power portable IC. To cope with the problem of leakage power, MTCMOS technology such as implementation of a sleep transistor has been proven effect in power reduction. However the existing Static Timing Analysis methods have not focused on this issue. This thesis presents a methodology for synthesizing a new Current Source Model from Spice models. Then with the newly synthesized Current Source Model, a complete procedure for the timing analysis of a circuit with inserted sleep transistor will be presented. In addition this procedure can be extended to account for the effect of IR drop during STA. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-12T17:53:13Z (GMT). No. of bitstreams: 1 ntu-97-R94943101-1.pdf: 2783189 bytes, checksum: f0c18d23bc3dd40c6ac8df9b6dc4f490 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Abstract III
Chapter 1 Introduction 1 Chapter 2 Relative Work 6 2.1 Resent Technology 6 2.2 CSM 7 Chapter 3 Make Data Library File by SPICE Simulations 9 3.1 Flow 10 3.2 Input 11 3.3 Current 12 3.3.1 Standard Cell and CSM 12 3.3.2 Input Slew and Dynamic current 14 3.3.3 Output Load and Dynamic Current 16 3.3.4 Get Current Table 17 3.4 Inner Capacitance 18 3.4.1 Parasitic Capacitance 19 3.4.2 Get Total Capacitance 20 3.4.2.1 Total Capacitance and Vo 21 3.4.2.2 Total Capacitance and Output Load 23 3.4.3 Get Final Capacitance Value 24 3.5 Output 24 Chapter 4 Make CSM Circuit File and Timing Analysis 26 4.1 Make CSM 26 4.1.1 Flow 27 4.1.2 Get Current and Capacitance Value 28 4.1.3 Fitting Current Table 28 4.2 Simulation with Sleep Transistor 34 4.3 Static Timing Analysis 35 4.3.1 Iterative Simulation Flow 36 4.3.2 Total Flow 37 Chapter 5 Experiment Result 39 5.1 Without Sleep Transistor 39 5.2 With Sleep Transistor 41 5.2.1 Before Inner Capacitance Recheck 41 5.2.2 After Inner Capacitance Recheck 42 5.3 Circuit Simulation 43 Chapter 6 Conclusion 44 reference 45 | |
| dc.language.iso | en | |
| dc.subject | 靜態時序分析 | zh_TW |
| dc.subject | 複合臨界電壓電路設計 | zh_TW |
| dc.subject | 睡眠電晶體 | zh_TW |
| dc.subject | 電流源模型 | zh_TW |
| dc.subject | 漏電流 | zh_TW |
| dc.title | 數位電路邏輯元件模型及時序分析 | zh_TW |
| dc.title | Current Source Model for Static Timing Analysis with Sleep Transistor | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 江介宏,黃鐘揚 | |
| dc.subject.keyword | 複合臨界電壓電路設計,睡眠電晶體,電流源模型,漏電流,靜態時序分析, | zh_TW |
| dc.subject.keyword | MTCMOS,sleep transistor,current source model,leakage power,timing analysis, | en |
| dc.relation.page | 47 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-03-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-97-1.pdf 未授權公開取用 | 2.72 MB | Adobe PDF |
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