低功率內容可定址記憶體之設計與分析

Abstract

對一個內容可定址記憶體的電路設計者言，大部分所面臨的挑戰是過高的功率消耗，本論文設計一個256行 × 144位元的內容可定址記憶體，主要是使用正回授定址線的方法來減少內容可定址記憶體的功率消耗。利用減少定址線動作時所耗的功率，相較於傳統的內容可定址記憶體電路設計，不但可以避免動態電路的諸多缺點，更可降低整個電路的功率消耗及增加比對速度。我們在0.18 μm 製程及1.8 V 的情況下，由模擬結果顯示出使用所提出的正回授定址線方法可達到0.9 ns的搜尋時間，與傳統NOR形式定址線的架構相比，在功率與延遲時間的乘積上可減少高達63%。最後，我們提出內容可定址記憶體完整的電路設計與分析， 並且與其他的電路設計做比較。

Content addressable memories (CAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of CAMs, high power consumption is one of the most critical challenges faced by CAM designers, This work proposes circuit techniques for reducing CAM power consumption. The main contribution of this work is reduction in match line (ML) sensing energy, and static-power reduction techniques. The ML sensing energy is reduced by employing positive-feedback ML sense amplifiers (MLSAs). We simulate the circuit with TSMC 0.18 μm process at 1.8 V. The simulation results of the postive-feedback MLSA show 86.3% reduction in ML power-delay product. Finally, design and analysis of a complete CAM circuit are presented, and compared with other published designs.