USB系統之匯流排功能性模組的驗證與實作

Abstract

隨著單晶片系統的設計複雜度增高，驗證成為整個設計流程的瓶頸。現今的驗證還是依據統模擬。但當系統的複雜度增加，模擬時間的增高將使得模擬的效率大為降低；正確性式晶片設計的主要目標，在特殊用途積體電路(ASIC)的設計中，功能性涵蓋率可以代表系統的正確性。如何有效減少模擬時間和增加系統的功能性涵蓋率，成為今日積體電路設計和驗證工程師所面臨的最大難題。 為了解決上述問題，本篇論文題出了一套USB的匯流排功能性模組(BFM)。在行為層級方面，匯流排功能性模組製定的標準相同。藉著測試電路的行為模式，模擬時間可以有效被控制。本文所設計的功能性模組接式可以被控制多項參數、以及可程式化的。所以我們可應用這些模組來建構USB的驗證環境。我們可以利用這個模組當範本：藉著傳送封包給欲測試的模組，接收測試模組的回傳封包來檢查欲測試模組的正確性。論文最後提出了驗證的環境，期望對於USB晶片設計者，能有更多幫助

Due to the increasing complexity of modern SoC designs, verification has become one of the bottlenecks of the entire IC design process [5]. Current verification strategy, based on traditional hardware simulation, is not able to fulfill designer’s need efficiently because of the escalation simulation time. Functional correctness is the most fundamental requirement for all hardware design. How to reduce the simulation time and increase the functional coverage are the primary issues that designers and researchers need to solve right away. In this thesis I provide a set of Universal Serial Bus (USB) Bus Functional Models (BFM), congruent to USB specification. By testing design under verification (DUV) in the behavior level, simulation time can be reduced. The BFM are configurable and programmable. We could construct all topologies of the USB system using the BFM. USB BFM can become a golden model, send packets to DUV, and receive packets from DUV to check if it’s functional correctly. Finally we will provide a USB simulation environment using USB BFM for designers to be a reference in chip or ip design .