使用倍數延遲鎖定迴路技術之時脈產生器

Abstract

傳統的倍數延遲鎖定迴路(Multiplying Delay-Locked Loop, MDLL)的鎖定行為，必須先利用一個外部重置訊號將全部延遲調整到最小延遲，再逐漸增加延遲來鎖定迴路，這是為了避免循環式延遲線所產生的全部延遲超過了相位偵測器的有效捕捉範圍，使延遲鎖定迴路的負迴授機制無法回復至其近似鎖定狀態，因此產生的時脈無法由低操作頻率轉換至高操作頻率，且輸出頻率範圍受到限制。 本論文提出應用於倍數延遲鎖定迴路時脈產生器的頻率偵測器，利用改良式頻率偵測器的選擇機制來解決上述提到的問題提出控制理論。並使用互補式金氧半電晶體0.35μm的製程以實做晶片且量測的方式來驗證想法。本設計可以產生37.5~444MHz的輸出時脈，不需額外的啟動控制電路即可將迴路鎖定在正確時脈頻率上，且可避免諧波鎖定等錯誤情況，因為本設計不需外部訊號來控制電路初始時的總延遲量，故可以相容於使用鎖相迴路時脈合成器作為內部時脈的系統。 接著針對頻率偵測器的邏輯電路再進行改良，提出一個新的頻率偵測器來鎖定迴路且改善缺點，簡單可行的電路架構更增加了實際上的應用性。

An external signal is necessary in the locking process of the traditional multiplying delay-locked loop. It is used to set total delay of the cyclic delay line in acquisition range of the phase detector, or the whole loop would be out of control. The output clock range of the clock synthesizer using cyclic pulse generation technique is limited by the acquisition range of the PD, and the clock synthesizer could not change its output clock frequency from low to high. An approach to solve the above question by using a phase detector with frequency selection is proposed in this thesis. The control algorithm of the approach is introduced and implemented in CMOS 0.35μm process to verify it. This circuit design can synthesize output clock frequency from 37.5MHz to 444MHz without extra start-up circuit and the external signal to control the initial total delay. This work overcomes the drawbacks of the clock synthesizer using MDLL technique, and is incorporated into the systems which use traditional PLL as clock synthesizer. More effects are done to simplify the circuit design and control algorithm in the rest part of the thesis, and the algorithm is verified by software tool, SIMULINK.