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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25475完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Jian-Feng Shiu | en |
| dc.contributor.author | 許健豐 | zh_TW |
| dc.date.accessioned | 2021-06-08T06:14:58Z | - |
| dc.date.copyright | 2007-02-27 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-01-31 | |
| dc.identifier.citation | [1] T. Cho and P. R. Gray, “A 10 b 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995
[2] F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 853–863, Nov. 1995. [3] Yuh-Min Lin, Beomsup Kim and Paul R. Gray,” A 13-b 2.5-MHz Self-calibrated Pipelined A/D Converter in 3-μm CMOS ,” IEEE J. Solid‐State Circuits, vol. 26, no. 4, pp. 628-636, Apr. 1991 [4] B.-S. Song et al., “A 12b 1 MHz capacitor error averaging pipelined A/D converter,” in ISSCC Dig. Tech. fapen, 1988, pp.226-227 [5] B.-S. Song, M. Tompsett, and K. Lakshmikumar,” A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D Converter,” IEEE J. Solid‐State Circuits, vol. 23 no. 6, pp. 1324-1333, Dec. 1988 [6] Hsin-Shu Chen, Bang-Sup Song , and Kantilal Bacrania ,” A 14-b 20-MSample/s CMOS Pipelined ADC,” in ISSCC Dig. Tech. Papers, 2001 [7] Hsin-Shu Chen, Bang-Sup Song , and Kantilal Bacrania ,” A 14-b 20-MSample/s CMOS Pipelined ADC,” IEEE J. Solid‐State Circuits, vol. 36, no. 6, pp.997-1001, Jun. 2001 [8] Hsin-Shu Chen, “ High-resolution nyquist-rate analog-to-digital converter,” Ph.D. dissertation, Univ. of Illinois at Urbana-Champaign, 2001 [9] Kurosawa. N, Kobayashi. H, Maruyama. K, Sugawara. H, Kobayashi. K, “ Explicit analysis of channel mismatch effects in time-interleaved ADC systems” Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 48, Issue 3, March 2001 Page(s):261 - 271 [10] Dyer K.C., Daihong Fu, Lewis S.H., Hurst P.J., “An analog background calibration technique for time-interleaved analog-to-digital converters” JSSCC of Volume 33, Issue 12, Dec. 1998 Page(s):1912 - 1919 [11] Jaeki, Yoo. Lee, E. Swartzlander, Jr. E.E.,”A digital background calibration technique for pipelined ADC using redundant stages” Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on Volume 1, 27-30 Dec. 2003 Page(s):5 - 8 Vol. [12] Sumanen, L.; Waltari, M.; Halonen, K.A.I.; “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter” JSSCC of Volume 36, Issue 7, July 2001 Page(s):1048 – 1055 [13] Waltari, M.; Halonen, K.;”Timing skew insensitive switching for double sampled circuits” ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 2, 30 May-2 June 1999 Page(s):61 - 64 vol.2 [14] Arias, J.; Boccuzzi, V.; Quintanilla, L.; Enriquez, L.; Bisbal, D.; Banu, M.; Barbolla, J.;”Low-power pipeline ADC for wireless LANs” Solid-State Circuits, IEEE Journal of Volume 39, Issue 8, Aug. 2004 Page(s):1338 – 1340 [15] Vaz, B.; Goes, J.; Paulino, N.;”A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency” VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on 17-19 June 2004 Page(s):432 - 435 [16] Yoshioka M., Kudo M., Gotoh K., Watanabe Y., “A 10b 125MS/s 40mW pipelined ADC in 0.18/spl mu/m CMOS” ISSCC. 2005 IEEE International 6-10 Feb. 2005 Page(s):282 - 284 [17] Hernes, B.; Briskemyr, A.; Andersen, T.N.; Telste, F.; Bonnerud, T.E.; Moldsvor, O.; “A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13/spl mu/m digital CMOS” 2004 ISSCC Feb. 2004 Page(s):256 - 526 Vol.1 [18] Abo, A.M.; Gray, P.R.;”A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter” Solid-State Circuits, IEEE Journal of Volume 34, Issue 5, May 1999 Page(s):599 - 606 [19]Byung-Moo Min; Kim, P.; Bowman, F.W., III; Boisvert, D.M.; Aude, A.J.;”A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC” Solid-State Circuits, IEEE Journal of Volume 38, Issue 12, Dec 2003 Page(s):2031 – 2039 [20] Jong-Bum Park; Sang-Min Yoo; Se-Won Kim; Young-Jae Cho; Seung-Hoon Lee; “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth” JSSCC of Volume 39, Issue 8, Aug. 2004 Page(s):1335 – 1337 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/25475 | - |
| dc.description.abstract | 近幾年無線通訊的發展，加速了生活數位化的進展，手機便是一個人手一機的產品，將來手機的趨勢為多功能，旣要可以上網，又要負責家庭安全的監控，也因此無線通訊協定WiMax大量的使用，WiMax需要高速的data rate(80MSPS以上)，這樣的規格需要一個高解析度且高速的類比數位轉換器。
由於低功率為手提式的無線通訊設備很重要的考量，但往往管線式類比/數位轉換器高速但卻要耗大功率，低功率卻沒辦法達到高速，因此要在一定的功率底下達到高速轉換是我們要研究的目標。 線性度為10-bit 速度大於200MS/s的類比數位轉換器常使用管線式類比/數位轉換器。在此希望設計一個操作在1.2V，線性度為10且轉換速度在每秒兩億五千萬次取樣頻率的類比數位轉換器。因此架構採用時間交錯式的管線式類比數位轉換器。 在第一章中，將介紹管線式類比數位轉換器的架構，並討論由電路非線性對轉換器造成的錯誤。在第二章中，時間交錯式的類比數位轉換器及在各通道間不匹配造成的錯誤將被介紹。在第三章中，說明一個新提出提升類比數位轉換器轉換速度的架構，並介紹各個重要電路的設計及模擬結果。第四章是量測的設定及量測結果。在第五章，我們將對這個電路做個總結。 | zh_TW |
| dc.description.abstract | In recent years, the improvement in wireless communication equipments speeds up the progress of digital life. Cell phone is an obvious example: everyone has a cell phone. The function of the cell phone tends to be versatile; it is not only used in internet but also used in taking care of home security. Thus, the WiMax protocol in wireless communication is always used. The Wimax needs high speed data rate and a high speed and high resolution ADC is required in the protocol.
Due to the portable equipments, low power is an important issue. But it conflicts between high speed and low power. Thus, it is an interesting topic to research in high speed and low power ADC. Pipelined ADC is always used in ADC with resolution larger than 10 bits and speed higher than 200MS/s. We wish to design a 1.2V 10-bit 250MS/s ADC, thus, a time-interleaved pipelined ADC architecture is chosen. Chapter 1 reviews the pipelined ADC architecture and introduces the errors in pipelined ADC. Chapter 2 discusses the time-interleaved ADC and the mismatch effects in time-interleaved ADC. A proposed architecture to increase conversion speed is given in Chapter 3 and the building blocks are also explained. Chapter 4 presents the test setup and measurement result. Final is a conclusion. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T06:14:58Z (GMT). No. of bitstreams: 1 ntu-96-R93943099-1.pdf: 2253920 bytes, checksum: c4fb197603c3589412c5322510a261e4 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 摘要…………………………………………………………………………………….i
Abstract………………………………………………………………………………ii Table of Contents……………………………………………………………………iii List of Figure…………………………………………………………………vi List of table………………………………………………………………….....viii Chapter 1 Pipelined A/D converter.......................…………………………..…1 1.1Motivation……………………………………………………………………1 1.2 Performance metrics……………………………………………………..2 1.2.1 Resolution…..………………………………………………………...2 1.2.2 Accuracy………………………………………………………………...2 1.2.3 Differential Nonlinearity (DNL)………………………………………...2 1.2.4 Integral Nonlinearity (INL)……………………………………………...3 1.2.5 Offset Error………………………………………………………………4 1.2.6 Gain Error………………………………………………………………..4 1.2.7 Signal-to-Noise ratio (SNR)……………………………………………..4 1.2.8 Total Harmonic Distortion (THD)……………………………………….5 1.2.9 Spurious-Free Dynamic Range (SFDR)…………………………………5 1.2.10 Signal-to-Noise and Distortion Ratio (SNDR)…………………………5 1.2.11 Effective Number of Bits (ENOB)……………………………………..6 1.3 Pipelined A/D converter…………………...…………………….…………….6 1.3.1 1.5-bit per stage architecture for 10bit pipelined ADC………………….7 1.4 Error sources in pipelined A/D converter..…………..……………………..….9 1.5 The techniques to cope with the errors in pipelined A/D converter………….12 1.5.1 Capacitor trimming.........................................................................12 1.5.2 Capacitor error average………………………………………………..12 Chapter 2 Time-interleaved Pipelined A/D converter…………………………..19 2.1 Introduction…………………………………………………………………..19 2.2 Time-interleaved ADC……………….………………………………….......19 2.3 Mismatches between channels……………………………………………….20 2.3.1 Offset mismatch effects...…………………………………….21 2.3.2 Gain mismatch effects……….……………………………………..22 2.3.3 Clock timing error effects….………………………………………...23 2.3.4 Combined channel mismatch effects………………………………..24 2.4 The techniques to deal with mismatches in time-interleaved pipelined ADC.. ………………………………………………………………………............26 Chapter 3 Proposed architecture to increase conversion speed ……………………28 3.1 Introduction…………………………………………………………………..28 3.2 The proposed architecture to increase conversion speed…………………28 3.3 High level circuit design…………………………………………………...31 3.4 System simulation………………………………………………………….31 3.5 Integrated circuit design……………………………………………………32 3.5.1 First stage MDAC……………………………………………………...32 3.5.2 Operational amplifier…………………………………………………..34 3.5.3 Comparator…………………………………………………………….35 3.5.3.1 Latch-type comparator…………………………………………...36 3.5.4 Operational amplifier bias circuit and CMFB circuit………………….38 3.5.5 Bootstrap sampling switch…………………………………………….39 3.6 Simulation results……………………………………………………………39 3.6.1 Operational amplifier simulation………………………………………39 3.6.1.1 AC analysis……………………………………………………….39 3.6.1.2 DC analysis………………………………………………………40 3.6.1.3 Transient analysis………………………………………………..41 3.6.1.4 First stage MDAC simulation result summary………………….41 3.6.2 FFT test………………………………………………………………..42 3.6.2.1 Summary of this work………………………………………………43 Chapter 4 Test Setup and Measurement results…………….……………………44 4.1 Introduction………………………………………………………………………44 4.2 Test Setup………………………………………………………………………...44 4.3 Print circuit board design……...…………………………………………………45 4.4 Experimental results……………………………………………………………...48 4.4.1 Static test…………………………………………………………………...50 4.5 Summary…………………………………………………………………………52 Chapter 5 Conclusions…………..………………………………………………..53 5.1 Conclusions…………………………………………………………………53 Bibliography ………………………………………………………………………...54 | |
| dc.language.iso | en | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | pipelined ADC | en |
| dc.title | 一個十位元每秒兩億五千萬次取樣管線式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit 250MS/s pipelined ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳怡然,洪士灝 | |
| dc.subject.keyword | 類比數位轉換器, | zh_TW |
| dc.subject.keyword | pipelined ADC, | en |
| dc.relation.page | 56 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2007-02-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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