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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24782完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Huang Jiun-Lang) | |
| dc.contributor.author | Yu-Tsung Liu | en |
| dc.contributor.author | 劉育宗 | zh_TW |
| dc.date.accessioned | 2021-06-08T05:56:23Z | - |
| dc.date.copyright | 2008-02-18 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-01-30 | |
| dc.identifier.citation | [1] C. Y. Kuo and J. L. Huang, ”A period tracking based on-chip sinusoidal jitter extraction technique ,” in VLSI Test Symposium, 2006.
[2] J. L. Huang, ”Random Jitter Testing Using Low Tap-Count Delay Lines,”Test Symposium, 2005. Proceedings. 14th Asian. [3] J. J. Huang and J. L. Huang, ”A low-cost jitter measurement technique for BIST applications,” in Asian Test Symposium, 2003, pp. 336-339. [4] Tian Xia, Hao Zheng, Jing Li, A. Ginawi, ”Self-refereed on-chip jitter measurement circuit using Vernier oscillators,” in Computer Society Annual Symposium, 2005, pp. 218-223. [5] A. H. Chan, G. W. Roberts, ”A jitter characterization system using a component-invariant Vernier delay line ,” in IEEE Transactions, Volume 12, Issue 1, Jan. 2004, pp. 79-95. [6] Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, L.-C. Wang, ”A scalable on-chip jitter extraction technique ,” in VLSI Test Symposium, 2004, pp. 267-272. [7] S. Sunter, A. Roy, ”BIST for phase-locked loops in digital applications,” in Test Conference, 1999, pp. 532-540. [8] C. K. Ong, D. Hong, K. T. Cheng, and L. C. Wang, ”Jitter spectral extraction for multi-gigahertz signal,” In Proc. Asia and South Pacific Design Automation Conference, 2004, pp. 298V303. 42 [9] A. Kuo, T. Farahmand, N. Ou, S. Tabatabaei, A. Ivanov, ”Jitter models and measurement methods for high-speed serial interconnects,” in ITC, 2004, pp. 1295-1302. [10] J. F. Buckwalter, and A. Hajimiri, Cancellation of Crosstalk-Induced Jitter, IEEE Journal of Solid-State Circuits,, March 2006, pp. 621-630. [11] LPM Quick Reference Guide, Altera, 1996. [12] Cyclone Device Handbook, Volume 1, Altera. [13] ITU-T G.810, ”Definitions and terminology for synchronisation networks”. [14] Tektronix technology, ”Understanding and Characterizing Timing Jitter”. [15] S. Tabatabaei, M. Lee, and F. Ben-Zeev, ”Jitter generation and measurement for test of multi-Gbps serial IO ,” ITC, 2004, pp. 1313-1321. [16] Bernd Laquai and Robert Schneider, Agilent Technologies, ”A cost effective method ofr jitter test of SERDES devices in high volume production,” Application notes. [17] S. Sunter, A. Roy, J.-F Cote, ”An automated, complete, structural test solution for SERDES ,” in International Test Conference, 2004, pp. 95-104. [18] T. J. Yamaguchi, M. Ishida, et al., ”A real-time jitter measurement board for high-performance computer and communication systems,” in International Test Conference, 2004, pp. 77-84. [19] F.J. Harris, ”On the use of windows for harmonic analysis with the discrete Fourier transform ,” in Proceedings of the IEEE Publication, 1978, pp. 51-83. [20] Darko Matovic and Cam Tropea, ”Spectral peak interpolation with application to LDA signal processing ,” IOP Publishing Ltd, 1991, pp. 1100-1106. [21] Agilent Technologies, ”Jitter Analysis: The dual-Dirac Model, RJ/DJ, and Q-Scale”, white paper. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24782 | - |
| dc.description.abstract | 本篇論文實現一個在晶片上可自我測試弦波抖動的方法。藉由累積分布函數的概念去解析弦波抖動，而後應用後置運算來加強對製程飄移的容忍。我們使用現場可程式化邏輯閘陣列來實現所設計的電路並應用任意波型產生器來產生所需的抖動訊源。與商業用自動化量測儀器比較，我們量測到的頻率錯誤率低於0.1%。當抖動的訊源頻率操作在較低的頻域，所量測到的振幅錯誤率則少於5%。 | zh_TW |
| dc.description.abstract | This study is to implement an on-chip sinusoidal jitter testing technique for design for test (DfT) application. The proposed technique utilizes cumulative density function
(CDF) based method to track the sinusoidal jitter, and applies post processing to enhance the process variation tolerance. We use FPGA to achieve the designed circuit, and employ an arbitrary waveform generator to inject jittery signal. Compared with the commercial automatic test equipment, the error ratio of jitter frequency is within 0.1%. When the jitter operates in lower frequency, the error ratio of jitter amplitude is less than 5%. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T05:56:23Z (GMT). No. of bitstreams: 1 ntu-97-J93921040-1.pdf: 20572076 bytes, checksum: 0154c189f55666273b02d01aaa0dd3e5 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 致謝 i
中文摘要 ii Abstract iii 1 Introduction 1 1.1 Motivation 1 1.2 Jitter Measurement with Test Equipment 1 1.3 Review of DfT/BIST Techniques 2 1.4 The Proposed Jitter Measurement Technique 2 1.5 Thesis Organization 3 2 Background 4 2.1 Jitter Definition 4 2.2 Jitter Categorization and Generation 6 2.3 Previous Measurement Method 9 3 The SJ Extraction Technique 15 3.1 Basic Idea 15 3.2 CDF-based Sampling 15 3.3 The SJ Extraction Architecture 16 3.4 The SJ Extraction Flow 17 4 FPGA Implementation of The SJ Extraction Circuit 21 4.1 The FPGA Platform 21 4.1.1 Features of CycloneTMEP1C20F400C7 21 4.1.2 Device Parameters 22 4.1.3 Development board 24 4.2 SJ Extraction Circuitry Implementation 24 4.3 FPGA Implementation 26 4.4 Tuning Multi Delay Taps 27 4.5 Jitter Generation 28 5 Experimental Results 30 5.1 Test Environment Setup 30 5.2 Jitter Source Measurement Results 32 5.3 Delay Line Measurement Results 32 5.4 Period Jitter Tracking Results 35 6 Conclusion 41 References 42 | |
| dc.language.iso | en | |
| dc.title | 以現場可程式化邏輯閘陣列實現弦波抖動之量測 | zh_TW |
| dc.title | FPGA Implementation of a Sinusoidal Jitter
Measurement Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成,李建模 | |
| dc.subject.keyword | 抖動,弦波抖動,現場可程式化, | zh_TW |
| dc.subject.keyword | jitter,SJ,FPGA, | en |
| dc.relation.page | 43 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2008-01-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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