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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Qi-Wei Kuo | en |
dc.contributor.author | 郭其偉 | zh_TW |
dc.date.accessioned | 2021-06-08T05:32:43Z | - |
dc.date.copyright | 2005-07-04 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-06-15 | |
dc.identifier.citation | REFERENCES
[1] R. P. Brent, H. T. Kung, 'A regular Layout for Parallel Adders' IEEE Trans., C-31(3):260-264, March 82. [2] P.M. Kogge, H. S. Stone, 'A Parallel Algorithm for the Efficient Solution of a Genera Class of Recurrence Equations”, IEEE Trans. on Computer Vol .C-22, No. 8, Aug., 1973. [3] T. Han, D. A. Carlson, 'Fast Area-Efficient VLSI Adders' 8th IEEE Symp. Computer Arithmetic, Como Italy, pp. 49-56, May 87. [4] S. Vangal et al, '5GHz 32b Integer-Execution Core in 130nm Dual-Vt CMOS' pp. 334-335, ISSCC 2002 [5] Chua-Chin Wang, Yih-Long Tseng, Po-Ming Lee, Rong-Chin Lee and Chenn-Jung Huang, “A 1.25GHz 32-Bit Tree-Structured Carry Lookahead Adder Using Modified ANT Logic” IEEE 2003. [6] A. Goldovsky, R. K. Kolagotla, C. J. Nicol and M. Besz, “A 1.0-nsec 32-bit Prefix Tree Adder in 0.25-um static CMOS” IEEE 1999. [7] Alexander Goldovsky, Hosahalli R. Srinivas, Ravi Kolagotla, and Rodney Hengst, “A folded 32-bit Prefix Tree Adder in 0.16-um static CMOS” Proc. 43rd IEEE Midwest Symp. On Circuit and System, Lansing MI, Aug 8-11, 2000. [8] Zhongde Wang, Graham A. Jullien, Willian C. Miller, Jinghong Wang and Sami S. Bizzan et al, “Fast Adders Using Enhanced Multiple-Output Domino Logic” IEEE 1997. [9] Utpal Desai1, Simon Tam, Robert Kim, Ji Zhang, Stefan Rusu,“ItaniumTM Processor Clock Design” [10] John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” [11] Matthew Ziegler and Mircea Stan, “Optimal Logarithmic Adder Structures with a Fanout of Two for Minimizing the Area-Delay Product” [12] Y.M. Huang James B. Kuo, “A new adder and multiplier architecture for low-voltage VLSI systems”, GIEE NTU 1999 [13] James B. Kuo and Jea-Hong Lou,“Low-Voltage CMOS VLSI Circuit”,Wiley 1999 [14] David Harris, ”Skew-Tolerant Circuit Design”, Morgan Kaufmann publishers, 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/24600 | - |
dc.description.abstract | 一個好的邏輯運算位元最重要的關鍵主要在於以下四點: (1) 運算頻率 (2) 延遲 (3) 消耗功率 (4) 時序可靠性。本篇論文中,我們採用了基板偏壓的方法將延遲-功率乘積作一最佳化。再者,由於製程越來越小,因製程或溫度變異所造成對時序的影響也越來越大。為了克服這個問題,我們在關鍵的時脈點上加入了多個可調延遲的緩衝器。至於加法器架構的選擇方面,我們採用了具有最小面積-延遲乘積的Han-Carlson加法器為基本架構,再用新的方法加以實現。為了供給此高速加法器一高頻訊號,一個鎖相迴路亦包含其中。此外基於量測考量,降頻及自我產生測試訊號的測試電路也是此計劃的一個重點。 | zh_TW |
dc.description.abstract | In this thesis, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18um bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purposes, and use a post-manufacture tunable clock structure that manipulates the clock at post-fabrication stage to compensate for the process dependent violation to the timing. Simulation results have shown that the substrate-bias optimization results in a 37% of power delay improvement and utilization of tunable delay elements achieve 50 ps of almost linear clock tunability.
A phase-locked loop and simple testing circuit also integrate into the chip for timing robustness and measurement purpose. Experiment results show the adder can successfully operate at 2.56GHz working frequency with 1.8V supply voltage. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T05:32:43Z (GMT). No. of bitstreams: 1 ntu-94-R92943088-1.pdf: 1247612 bytes, checksum: 9200de086d21c7e436f19c5414e9f28c (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Table of Contents
Chapter 1 Introduction 1 1-1 Motivation 1 1-2 Organization 2 Chapter 2 Background of the Adder 4 2-1 Introduction 4 2-2 Conventional adders 4 2-3 Prefix adders 7 2-3.1 Brent-Kung adder 9 2-3.2 Koggy-Stone adder 12 2-3.3 Han-Carlson adder 13 2-4 Summary 16 Chapter 3 Design Considerations and Architecture of the Adder 17 3-1 Introduction 17 3-2 Propagate and generate signal generating stage 17 3-3 Carry-merge tree 18 3-4 Sum signal generating stage 21 3-5 Clock distribution 22 3-5.1 Domino logic timing analysis 23 A. Rising setup analysis 23 B. Falling setup analysis 23 C. Rising hold analysis 24 D. Falling hold analysis 25 3-5.2 Skew-tolerant design 26 3-5.3 Clock tree implementation 31 3-6 Simulation result 32 3-7 Summary 33 Chapter 4 Substrate-Bias Optimized 0.18um 2.5GHz 32-bit 34 Adder with Post-Manufacture Tunable Clock 4-1 Introduction 34 4-2 Substrate bias 34 4-2.1 Threshold voltage and body effect 34 4-2.2 Substrate bias and delay-power product 40 4-3 Post-Manufacture Tunable Clock 43 4-3.1 Process/temperature variation induced clock skew 43 4-3.2 Circuit design and simulation result 44 4-4 Phase-locked loop 45 4-4.1 Review of PLL 45 4-4.2 Phase-frequency detector 48 4-4.3 Charge pump and loop filter 50 4-4.4 Voltage-controlled oscillator 53 4-4.5 Frequency divider 54 4-4.6 Third order PLL 55 4-5 Considerations and procedures of the system 56 4-5.1 PLL 56 4-5.2 Adder 57 4-5.3 Testing Circuitry 57 4-5.3.1 Linear feedback shift register 58 4-5.3.2 Timing issues 59 4-5.3.3 Testing method 60 4-5.4 Simulation result 61 4-6 Experimental result 62 4-7 Summary 64 Chapter 5 Conclusions 65 REFERENCES 66 | |
dc.language.iso | en | |
dc.title | 基板偏壓與抗時脈不精確之32位元高速加法器 | zh_TW |
dc.title | Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳良基,李鎮宜 | |
dc.subject.keyword | 加法器,基板偏壓, | zh_TW |
dc.subject.keyword | adder,substrate bias,PVT variation, | en |
dc.relation.page | 67 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2005-06-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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