一個具有新切換方式補償拋物線誤差之10位元互補式金氧半電流切換式數位類比轉換器

Abstract

這篇論文提出了一個十位元250百萬赫茲的電流切換式數位類比轉換器，它使用的是雙倍區段化的架構，其中包含了五位元的高位元，中間兩位元的高位元以及最後用來當成控制二進制電流源的三位元。這樣的設計不僅可以保持原本電流切換式架構的優點，更可以達到降低功率消耗的好處。在這篇論文中我們實現了兩種數位類比轉換器，一個是使用二維切換方式，另一種是使用我們所提出的切換方式來實現。這個新的切換方式是將高位元的電流源分成八個部份來補償拋物線誤差並且使用數狀圖來達到最佳化的目的。

這個數位類比轉換器是使用UMC 0.18微米混合信號互補式金氧半製程來實現。它的差動非線性失真及整體非線性失真分別為0.2LSB及0.7LSB。當操作在200百萬赫茲及輸入頻率為1百萬赫茲時，SFDR達到64dB。功率消耗在1.8伏特操作之下為20毫瓦。整體晶片的核心面積為0.72x0.68mm2 。

This thesis proposes a 10 bit 250MHz current steering DAC with a doubly segmented current steering architecture that consists of two parts: upper 5 bit MSBs and intermediate 2 bit MSBs. The other 3 bit LSBs are binary weighted current source. This design not only keeps the advantages of current steering architecture, but also consumes lower power. Two types of DACs are implemented. One is implemented by a two-dimension switching scheme, another one is implemented by the proposed switching scheme. The new switching scheme divides the MSB current source into eight parts to compensate parabolic error and also use tree structure to optimize. This DAC is to be implemented with a UMC 0.18 µm 1P6M mixed signal CMOS process. The DNL and INL are 0.2 and 0.7 LSB, respectively. The SFDR is 64dB when the update rate is 200MHz and the input frequency is 1MHz. The power consumption is 20 mW, and it operates from 1.8V. The active area is 0.72x0.68mm2.