使用0.18-μm CMOS製程實作應用於GNSS之全積體化雙頻離散時間接收機

Abstract

本論文著重在GNSS中的L1（1.57542 GHz）以及L5（1.17645 GHz）頻段的訊號，皆屬於CDMA（Code-Division Multiple Access）；本接收機可以接收總共十一種訊號。由於功能的需求不同，擁有不同訊號的頻寬，分別是4.092 MHz（L1）以及10.23 MHz（L5）。考量到GNSS的訊號相較於一般通訊系統的訊號要來的微弱（-130 dBm），對於flicker noise（對於先進製程而言，其corner frequency ~ 1 MHz）的影響更加嚴重，進而造成sensitivity降低。架構上採用low-IF（Intermediate Frequency）來避開它。在射頻電路的部分，低雜訊放大器（LNA）可以控制欲接收的頻段，之後由image-rejecting mixer將RF訊號下降至所需要IF的位置；在類比頻段的部分，我們採用了離散時間濾波技術（discrete-time filtering technique），藉由數位電路控制可程式化的電容陣列，實現了可調整頻寬的濾波器。本接收機的可程式特性可以搭配DSP（Discrete-time Signal Processing）的需求做切換，即使在失去對特定系統衛星的追蹤時，可以迅速切轉並接收另一個系統的訊號。讓整體效能提升！ 我們採用了0.18-μm CMOS製程設計與實現了一顆全積體化的接收機：從射頻的LNA，image-rejecting mixer，以及產生特定頻率的頻率合成器，到類比頻段可調整接收頻寬的離散時間濾波器。尤其在濾波器方面：（1）藉由數位控制，可濾出頻寬4.092 MHz以及10.23 MHz的訊號；（2）優異的抗製程變異特性，讓模擬和實作之間的差異可以減小；（3）使用較少類比元件的天性，使得我們的接收機隨著製程演進可以降低成本；（4）利用數位操作的獨特性，在靜態上不耗電！

The thesis focuses on the L1 (1575.42 MHz) and L5 (1176.45 MHz) bands in GNSS, which are all CDMA (Code-Division Multiple Access) systems; total 11 different signals can be captured by our receiver. Because of different applications, the signal bandwidth is different; they are 4.092 (L1) and 20.46 (L5) MHz. As the GNSS signals are relatively weak (-130 dBm) comparing to other communication systems, the flicker noise (corner frequency ~ 1 MHz in advanced process) has a big impact on the signals and then degrades the sensitivity. Our receiver is low-IF (Inter-mediate Frequency) architecture, which can avoid the low-frequency noise after down-conversion. In RF (Radio Frequency) part of the receiver, the LNA (Low-Noise Amplifier) can select wanted band and the image-reject mixer will down-converts the RF signal to required IF location. In analog part, we use the discrete-time (D.T.) filtering technique to design and implement a bandwidth-reconfigurable filter by digitally controlling a switched-capacitor array. The reconfigurability of the receiver can be controlled by the DSP (Digital-Signal Processing). When we lose the tracking to arbitrary satellites, the receiver can rapidly switch and re-track the signals which are more environmentally-resistive. Therefore, the overall performance can be enhanced! We use 0.18-μm CMOS process to design and implement a fully-integrated receiver, which includes a switchable dual-band LNA and image-reject mixer at RF, a frequency synthesizer, and bandwidth-reconfigurable D.T. filter. Especially in the D.T. filter, (1) we can filter out 4.092-MHz and 10.23-MHz signals by digital control; (2) excellent process tolerance keeps the difference between simulation and implementation small; (3) with less analog components, the cost of our design will be reduced following the process migration; (4) due to digital control, no static power consumption!