CMOS微型位移電容感測器之電路設計與製作

Abstract

本論文的主旨是探討CMOS微型位移電容感測器之輸出電壓與電容改變量的關係，在實現CMOS位移電容感測器之佈局圖後，將此佈局圖下線並做出實體晶片，接著量測此晶片並分析各節點訊號，進一步討論內部元件運作情形是否正常。本晶片主要是用摺疊疊接式放大器做為主體，接著佈局離散元件，最後接上pad完成佈局圖，下線做出實體晶片後加以量測並改正。 本論文使用國家晶片系統設計中心(NSC Chip Implementation Center, CIC )所提供的台灣積體電路(TSMC)0.35微米 Mixed-Signal 2P4M Polycide3.3/5V的製程，並使用Synopsys公司出的Hspice電路模擬軟體與思源公司的laker軟體進行模擬及佈線。

The theme of the thesis is to discuss the relation of the output voltage and the variance of capacitance about CMOS displacement capacitive sensors. Design and completion of the layout is the first step of the procedure flow. According to the layout the IC is taped out. The last step is to measure and to analyze the signals from every nodes. Through the whole procedure flow, the components which are workable can be defined. This circuit is composed of folded-cascode amplifiers and dispersed elements. The chip can be measured after taping out the IC. In this thesis, we apply 0.35 Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSMC which is provided by NSC Chip Implementation Center. Finally, we use Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout the circuit.