一個低功率子範圍循序漸進式類比數位轉換器

Abstract

隨著科技的進步，無線通訊產品也益發的普及到我們日常生活中。在各式無線通訊系統中，藍芽系統更是在其中扮演重要的角色。又因為可攜帶式電子產品的要求，低功率消耗成為設計類比數位轉換器時的必要考量。本論文依據傳統的循序漸近式架構(Successive-Approximation Register)，融合子範圍(Sub-range)的概念。在前面比較裡降低對準確度的要求，進而提升比較速度。再利用重疊動作(Overlap action)把之前比錯的地方校正回來。實現一個12位元的解析度與一千萬赫茲的轉換速度的低功率循序漸進式類比數位轉換器(Successive-Approximation Analog-to-Digital Converter)，來應用在藍芽系統(Bluetooth System)中。本設計採用台積電0.13微米1P8M的製程，晶片操作在10MS/s的取樣頻率，奈奎斯特輸入訊號頻率下，SNDR為59.7dB，SFDR為69.8dB，核心電路功率消耗為3mW。晶片總面積為1.19mm2，核心電路部分約為0.096mm2。

As a result of rapidly improve in the technology, wireless communication devices become more popular in our daily life. Among various wireless communication systems, Bluetooth system plays an important role in that. Because of requirement of portable electrical products, power consumption becomes an essential criterion in the design of Analog-to-Digital Converter (ADC). This thesis presents a method combine traditional Successive-Approximation architecture with Sub-range concept. By this way, we can relieve accuracy requirement on the MSB array and heaving total conversion rate. Then we use overlap action to correct error exist in the MSB comparison. A 12-bit 10MS/s low power consumption Successive-Approximation Analog-to-Digital Converter applied for the Bluetooth system is proposed. This design adopted TSMC 0.13-um 1P8M CMOS process. While the chip operates at sampling rate 10MS/s and Nyquist rate input frequency, the SNDR and SFDR achieve 59.7dB and 69.8dB respectively. The power consumption of core circuit is 3mW. The chip with pads occupies 1.19mm2 and the core area is about 0.096 mm2.