使用多位元正反器以節省時脈功率

Abstract

近年來便攜式設備的興起，低功率電路設計成為現今設計中最被注目的問題。由先前的設計經驗得知，時鐘樹為整體電路中最為消耗功率的元件之一，降低時鐘樹的消耗功率可以有效的降低整體的消耗功率。因此，許多關於低功率時鐘樹的設計一一被提出。 另外，隨著製程的日益先進，最小的反相器已不止能驅動一個單一位元正反器。因此，多個單一位元正反器分享同一驅動，也就是使用多位元正反器，將可有效的減少反相器的使用，進而減少整體使用在其上的功率及面積。另一方面，亦可有效的縮小時鐘樹的總線長，進而亦降低時鐘樹的消耗功率。 本論文所提出之演算法，可使設計功率有效降低。其中包含正反器功率節省平均約23%，時鐘樹功率節省平均約48%。另外，本演算法用於合併兩百萬個正反器最快不到一個小時就能完成，整體實驗時間複雜度為Θ(n1.052)，比Θ(nlogn)的實驗時間複雜度Θ(n1.09)較為小。因此為一有效率之演算法。

In the recent years, low-power circuit design has become the most concerned issue in today’s design problems due to the popularity of the portable devices. From the previous design experience, the clock tree is one of the most power consumption components of the whole design. Reducing the power consumption of the clock tree can effectively reduce the overall power consumption. Therefore, many techniques on low-power clock tree design have been proposed. In addition, with increasingly sophisticated manufacturing process, the smallest inverter usually can drive more than a 1-bit flip-flop. Therefore, several 1-bit flip-flops can share the same drive, that is, the multi-bit flip-flops. It will effectively reduce the use of inverter, thereby reducing the overall power consumption and chip area. On the other hand, it can also effectively reduce the clock tree wire length, and thus also reduce the clock tree power consumption.

The algorithm in this work can effectively reduce the total power of the designs. The power saving includes the flip-flops power saving, about 23%, and clock tree power saving, about 48%. On the other hand, merging 2,000,000 flip-flops with this algorithm can be achieved in least than 1 hour. The empirical time complexity of the algorithm is Θ(n1.052) which is less than the empirical time complexity of Θ(nlogn) time complexity algorithm.