應用於物聯網之極低功耗鎖相迴路及石英震盪器設計

Abstract

時脈產生器是現代物聯網系統中一項不可或缺的重要組成。為了延長系統裝置中電池的使用壽命，在時脈產生器的設計裡功耗尤其關鍵。本篇論文提出了一極低功耗之32.768 kHz之分數型鎖相迴路，以及一雙輸出之石英時脈產生器，來達成低功耗之運作。 第一個作品為一極低功耗之32.768 kHz之分數型鎖相迴路，可應用於石英震盪器及微機電系統震盪器中，協助其產生32.768 kHz時鐘。本作品主要特色在於以一時序機制控制充電泵的開關，大幅省下充電泵在閒置時所消耗的功率，並以一CMOS擬態電阻來實現壓控震盪器中的大阻值電阻，將迴路中的電流控制在一個極小的值，同時大幅縮小晶片面積。此外，透過一電壓穩壓器提供一個較低的電壓，作為迴路中數位電路區塊的電源電壓，以降低數位電路的功率消耗。本作品以TSMC 180-nm製程實現，核心面積為0.116 mm2，在1V電壓源下總消耗電流為169nA，峰對峰抖動(peak-to-peak jitter)為529.4 ns。 在第二個作品中，我們提出了一個極低功耗雙輸出之石英時脈產生器，它僅通過一個石英晶體即提供出26-MHz和32.768-kHz時鐘，滿足了現代物聯網應用中小型化和低功耗的需求。我們採用自充式的架構，並提出一工作週期功耗調控技術來實現低功耗之26-MHz石英震盪器，並使用第一個作品中提出的分數型鎖相迴路來產生32.768 kHz時鐘。本作品採用TSMC 90-nm CMOS製程製造，核心面積為0.18 mm2，在1V電壓源下總消耗電流為1.41 μA。

Clock generators are significant components to produce the timing signals in modern Internet of Things (IoT) systems. To enable long battery lifetime, power consumption is a critical concern in clock generators. In this thesis, an ultra-low power 32.768-kHz fractional-N PLL and a dual-output quartz crystal clock generator are proposed for low-power clock generation. In the first work, we propose an ultra-low power 32.768-kHz fractional-N PLL which can be applied in both crystal and MEMS-based oscillators. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a pseudo-resistor is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore, the digital power consumption is reduced by operating the digital circuits at a lower supply voltage generated from an on-chip voltage regulator. This PLL is fabricated in the TSMC 180-nm CMOS process with a core area of 0.116 mm2. Its current consumption is 169 nA from a 1-V supply. The measured peak-to-peak cycle-to-cycle jitter is 529.4 ns. In the second work, we propose an ultra-low power dual-output quartz crystal clock generator. It provides both 26-MHz and 32.768-kHz clocks by only one crystal, which meets the demand for miniaturization as well as power reduction in modern IoT applications. We adopt a self-charged architecture with a proposed duty-cycled power control technique to realize a low-power 26-MHz crystal oscillator, and use the fractional-N PLL proposed in the first chip to perform the 32.768 kHz clock generation. This clock generator is fabricated in the TSMC 90-nm CMOS process with a core area of 0.18 mm2. Its current consumption is 1.41 μA from a 1-V supply.