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Title: | 具製程、電壓與溫度背景校正之倍頻延遲鎖定迴路 A PVT-Tolerant MDLL with a Background Coarse-Frequency Selector and a Frequency Calibrator using a Delay-Calibrated SSPD |
Authors: | Yu-Kai CHIU 邱鈺凱 |
Advisor: | 劉深淵(Shen-Iuan Liu) |
Keyword: | 鎖相迴路,倍頻延遲鎖定迴路,頻率合成器, Phase-Locked Loop,Multiplying Delay-Locked Loop,Frequency Synthesizer, |
Publication Year : | 2019 |
Degree: | 碩士 |
Abstract: | 本論文實現一具製程、溫度與電壓背景校正之倍頻延遲鎖定迴路,為了降低參考突波與相位抖動,本論文提出一具延遲校正之次取樣相位偵測器來校正頻率誤差,其中相位偵測器與電荷泵的相位雜訊不會被放大N2倍,為了增加迴路的頻率涵蓋與降低製程、溫度與電壓所造成的非理想效應,本論文也提出一背景執行之頻率選擇器,本論文已於台積電40奈米製程實踐與驗證,本電路輸出時脈為2.4GHz,其輸入參考頻率為150MHz,電路佈局面積為0.0135 mm2,於1V之工作電壓下,總功率消耗為5.2mW,量測之方均根抖動量為229fs,參考突波為-54.3dBc。 A multiplying delay-locked loop (MDLL) with a background coarse-frequency selector and a frequency calibrator is presented. To reduce the reference spur due to the frequency error, a frequency calibrator using a delay-calibrated SSPD is presented. The phase noise of the CP and the SSPD is not multiplied by N2. To cover a wide frequency variation, the background coarse-frequency selector is also presented. This MDLL is fabricated in 40-nm CMOS technology. The active area is 0.013mm2, and the power consumption is 5.2mW from a supply of 1V. It exhibits a root-mean-square jitter of 229fs at 2.4GHz output and the reference spur of -54.3dBc under a reference clock of 150MHz. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21813 |
DOI: | 10.6342/NTU201900154 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-108-1.pdf Restricted Access | 4.28 MB | Adobe PDF |
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