具展頻追蹤與較佳高頻抖動容忍度之5-Gb/s數位時脈資料回復電路

Abstract

近幾年來，人們對於有線資料傳輸速度的要求愈來愈高。而有線傳輸技術也持續以指數的方式成長。然而，隨著資料傳輸的速度愈來愈高，其所產生的電磁干擾問題也愈嚴重。因此，展頻時脈技術被應用來降低高頻時脈所帶來的電磁干擾。然而，展頻時脈技術會使得時脈頻率隨時間變化。此頻率變化所造成的相位誤差會對時脈資料回復電路造成負擔並進而劣化高頻抖動容忍度甚至脫鎖。 本論文提出一適用於資料帶有展頻時脈下的5-Gb/s數位時脈資料回復電路。透過適當的迴路參數設計以及所提出的積分增益控制器，除了可追蹤展頻外，並可降低因展頻時脈造成的相位誤差並進而提升高頻抖動容忍度。此電路實作於40奈米CMOS製程，其面積與功耗分別為0.022 mm2與9.9 mW。在給定27-1帶有±300 ppm頻率誤差以及-5000ppm展頻時脈的5-Gb/s PRBS下，透過提出的積分增益控制器，在位元錯誤率小於10-12時，最小的高頻抖動容忍度可提升至0.55 UIpp。

The high-speed wireline communication is in high demand for people and keeps exponential growth in recent years. However, the problem of electromagnetic interference (EMI) caused by high-frequency clock becomes more severe when the data rate becomes higher. Hence, the spread-spectrum clocking (SSC) technique is specified to reduce the EMI. However, the SSC makes the clock frequency vary with time. The phase error caused by the frequency deviation will impose a burden on the clock and data recovery (CDR) circuit, deteriorate the high-frequency jitter tolerance (JTOL), and even make the CDR circuit out of lock. In this thesis, a 5-Gb/s digital CDR (DCDR) circuit which is applicable to the input data with SSC is proposed. By the proper design of loop parameter and the proposed integral gain controller, the DCDR circuit is able to track the input data with SSC and the phase error is reduced. The high-frequency JTOL of the DCDR circuit is enhanced accordingly. This circuit is fabricated in 40-nm CMOS process. Its active area is 0.022 mm2 and the power consumption is 9.9 mW. For a 5-Gb/s PRBS of 27-1 with frequency offset of ±300 ppm and SSC of -5000ppm, the minimum high-frequency JTOL with a bit error rate < 10-12 is improved to 0.55 UIpp by using the proposed integral gain controller.