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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21480完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Shun-Chi Chang | en |
| dc.contributor.author | 張舜棋 | zh_TW |
| dc.date.accessioned | 2021-06-08T03:35:19Z | - |
| dc.date.copyright | 2019-08-06 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-07-31 | |
| dc.identifier.citation | [1] “Universal serial bus 3.0 specification”, Revision 1.0, Nov. 2008.
[2] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in IEEE International Symposium on Electromagnetic Compatibility, Aug. 1994, pp. 227-231. [3] H. J. Jeon, R. Kulkarni, Y. C. Lo, J. Kim, and J. S. Martinez, “A bang-bang clock and data recovery using mixed mode adaptive loop gain strategy,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1398-1415, Jun. 2013. [4] J. Y. Lee, J. H. Yoon, and H. M. Bae, “A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 8, pp. 2466-2472, Aug. 2014. [5] S. W. Kwon et al., “An automatic loop gain control algorithm for bang-bang CDRs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 12, pp. 2817-2828, Dec. 2015. [6] J. Liang, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi, “Loop gain adaptation for optimum jitter tolerance in digital CDRs,” IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2696-2708, Sep. 2018. [7] G. R. Gangasani et al., “A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2474-2489, Nov. 2014. [8] H. Pan et al., “A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 442-443. [9] T. Yoshikawa, T. Hirata, T. Ebuchi, T. Iwata, Y. Arima, and H. Yamauchi, “An over-1-Gb/s transceiver core for integration into large system-on-chips for consumer electronics,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 9, pp. 1187-1198, Sep. 2008. [10] J. L. Sonntag and J. Stonick, “A digital clock and data recovery architecture for multi-gigabit/s binary links,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006. [11] S. Ryu, S. Son, and J. Kim, “An accurate and noise-resilient spread-spectrum clock tracking aid for digitally-controlled clock and data recovery loops”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 3, pp. 1245-1257, Mar. 2019. [12] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sep. 2004. [13] L. Rodoni, G. Buren, A. Huber, M. Schmatz, and H. Jackel, “A 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 1927-1941, Jul. 2009. [14] C. W. Tien and S. I. Liu, 'A digital phase-locked loop with background supply voltage sensitivity minimization', IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 6, pp. 1830-1839, Jun. 2018. [15] P. K. Hanumolu et al., A wide-tracking range clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008. [16] B. Nikolic et al., “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun. 2000. [17] J. Cao et al., “OC-192 transmitter and receiver in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1768-1780, Dec. 2002. [18] G. Wu et al., “A 1-16 Gb/s all-digital clock and data recovery with a wideband high-linearity phase interpolator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 7, pp. 2511-2520, Jul. 2016. [19] E. Monaco et al., “A 2–11 GHz 7-bit high-linearity phase rotator based on wideband injection-locking multi-phase generation for high-speed serial links in 28-nm CMOS FDSOI,” IEEE J. Solid-State Circuits, vol. 52, no. 7, pp. 1739-1751, Jul. 2017. [20] J. F. Bulzacchelli et al., “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006. [21] L. Kong, Y. Chang, and B. Razavi, “A 14 μm × 26 μm 20-Gb/s 3-mW CDR circuit,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2018, pp. 271-272. [22] M. Pozzoni et al., “A multi-standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1306-1315, Apr. 2009. [23] W. C. Chen et al., “A 2.5-8Gb/s transceiver with 5-tap DFE and second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2010, pp. 1-4. [24] P. A. Francese et al., “A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2490-2502, Nov. 2014. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21480 | - |
| dc.description.abstract | 近幾年來，人們對於有線資料傳輸速度的要求愈來愈高。而有線傳輸技術也持續以指數的方式成長。然而，隨著資料傳輸的速度愈來愈高，其所產生的電磁干擾問題也愈嚴重。因此，展頻時脈技術被應用來降低高頻時脈所帶來的電磁干擾。然而，展頻時脈技術會使得時脈頻率隨時間變化。此頻率變化所造成的相位誤差會對時脈資料回復電路造成負擔並進而劣化高頻抖動容忍度甚至脫鎖。
本論文提出一適用於資料帶有展頻時脈下的5-Gb/s數位時脈資料回復電路。透過適當的迴路參數設計以及所提出的積分增益控制器，除了可追蹤展頻外，並可降低因展頻時脈造成的相位誤差並進而提升高頻抖動容忍度。此電路實作於40奈米CMOS製程，其面積與功耗分別為0.022 mm2與9.9 mW。在給定27-1帶有±300 ppm頻率誤差以及-5000ppm展頻時脈的5-Gb/s PRBS下，透過提出的積分增益控制器，在位元錯誤率小於10-12時，最小的高頻抖動容忍度可提升至0.55 UIpp。 | zh_TW |
| dc.description.abstract | The high-speed wireline communication is in high demand for people and keeps exponential growth in recent years. However, the problem of electromagnetic interference (EMI) caused by high-frequency clock becomes more severe when the data rate becomes higher. Hence, the spread-spectrum clocking (SSC) technique is specified to reduce the EMI. However, the SSC makes the clock frequency vary with time. The phase error caused by the frequency deviation will impose a burden on the clock and data recovery (CDR) circuit, deteriorate the high-frequency jitter tolerance (JTOL), and even make the CDR circuit out of lock.
In this thesis, a 5-Gb/s digital CDR (DCDR) circuit which is applicable to the input data with SSC is proposed. By the proper design of loop parameter and the proposed integral gain controller, the DCDR circuit is able to track the input data with SSC and the phase error is reduced. The high-frequency JTOL of the DCDR circuit is enhanced accordingly. This circuit is fabricated in 40-nm CMOS process. Its active area is 0.022 mm2 and the power consumption is 9.9 mW. For a 5-Gb/s PRBS of 27-1 with frequency offset of ±300 ppm and SSC of -5000ppm, the minimum high-frequency JTOL with a bit error rate < 10-12 is improved to 0.55 UIpp by using the proposed integral gain controller. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T03:35:19Z (GMT). No. of bitstreams: 1 ntu-108-R04943014-1.pdf: 8785951 bytes, checksum: 5a9673fee495f9a849dc2000c2fd1892 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 1. Introduction………………………………………………………… 1
1.1 Overview…...………………………………………………... 1 1.2 Wireline Communication...………………………………….. 1 1.3 Clock and Data Recovery Circuit…......................................... 3 1.3.1 Advantage of Digital CDR Circuit……...…………… 3 1.3.2 Advantage of Phase-Interpolator-Based CDR Circuit. 4 1.3.3 Jitter Tolerance………………………………………. 5 1.4 Spread-Spectrum Clocking…...……………………………… 6 1.4.1 Problem of EMI and Reduction Techniques…………. 7 1.4.2 Specification of Spread-Spectrum Clocking………… 7 1.5 Thesis Organization….………………………………………. 8 2. A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency JTOL…………………….…………... 9 2.1 Motivation…………………………………………………… 9 2.2 Jitter Tolerance Analysis...…………………………………... 11 2.2.1 JTOL 3dB Corner Frequency………………...……… 11 2.2.2 SSC Capability……………………..………………... 14 2.2.3 High-Frequency JTOL Enhancement…….………….. 16 2.2.4 Behavioral Simulation Results………………………. 16 2.3 Circuit Description…………………………………………... 22 2.3.1 DCDR………………………………………………... 22 2.3.2 The KI Controller…………………………………….. 23 2.3.3 Data/Edge Sampler and 2:16 Demultiplexer………… 29 2.3.4 Divider and Low-Pass Filter………………………… 33 2.3.5 Phase Interpolator……………………………………. 37 3. Measurement Setup and Experimental Results………….……….. 39 3.1 Die Photo and Power Breakdown….…………….................... 39 3.2 Measurement Setup...………………………………………... 40 3.3 Experimental Results..……………………………………….. 41 3.4 Performance Summary………………………………………. 50 3.5 Additional Experimental Results and Discussions…………... 51 4. Conclusion and Future Work……………………………………… 55 4.1 Conclusion…………………………………………………… 55 4.2 Future Work………………………………………………….. 56 Bibliography ……………………………………………………………….. 57 | |
| dc.language.iso | en | |
| dc.title | 具展頻追蹤與較佳高頻抖動容忍度之5-Gb/s數位時脈資料回復電路 | zh_TW |
| dc.title | A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency JTOL | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee),陳開基(Kai-Ji Chen) | |
| dc.subject.keyword | 時脈資料回復,展頻時脈,相位內插器,高頻,抖動容忍度, | zh_TW |
| dc.subject.keyword | Clock and data recovery,spread-spectrum clocking,phase interpolator,high-frequency,jitter tolerance, | en |
| dc.relation.page | 59 | |
| dc.identifier.doi | 10.6342/NTU201901128 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2019-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-108-1.pdf 目前未授權公開取用 | 8.58 MB | Adobe PDF |
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