請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21139
標題: | 欠疊型環繞式閘極場效電晶體之非對稱側壁設計 Asymmetric Spacer Design for Underlap Gate-All-Around Field-Effect Transistors |
作者: | Yuan-Po Lin 林淵博 |
指導教授: | 黃定洧(Ding-Wei Huang) |
關鍵字: | 環繞式閘極場效電晶體,欠疊結構,高介電係數材料,側壁,次臨界擺幅,汲極引發位能障下降,閘極邊緣電場引發位能障下降, Gate-All-Around Field-Effect Transistors,Underlap Structure,High-κ Material,Spacer,Subthreshold Swing,Drain Induced Barrier Lowering,Gate Fringe-Induced Barrier Lowering, |
出版年 : | 2019 |
學位: | 碩士 |
摘要: | 傳統金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistors, MOSFET)隨著摩爾定律(Moore’s Law)的進展持續微縮,導致閘極對通道的控制能力降低引起短通道效應(Short Channel Effects, SCE)產生。為了提升閘極對通道的控制能力及抑制短通道效應,發展出鰭式場效電晶體(Fin Field Effect Transistors, FinFET),使得半導體工業產生重大突破。為了進一步提升元件效能及抑制短通道效應,環繞式閘極場效電晶體由於其具有最大的表面積與體積比(Surface-to-Volume Ratio),具有比 FinFET 更優異的元件效能及閘極對通道控制能力,而被認為是下一世代得以取代 FinFET 的候選結構。
本論文研究參考 5 nm 技術節點之低功率環繞式閘極場效電晶體之結構參數,使用欠疊結構(Underlap Structure)以抑制漏電流的產生,然而由於欠疊結構使通道電阻上升會導致導通電流急遽衰退而降低元件效能。因此,需搭配高介電常數材料製作側壁(Spacer)以提升閘極邊緣電場(Gate Fringing Field)耦合至欠疊區域降低電阻值。然而高介電常數的側壁也會導致較高的閘極電容,使元件本質延遲時間增加,因此採用雙重側壁結構設計,藉由真空製作的外部側壁與 HfO2 製作的內部側壁,可以同時降低閘極電容並進一步提升元件電性表現。雙重側壁結構材料選擇完畢後對側壁長度及高度進行優化,並求得 Linner = 3.75 nm、Hinner = 6.00 nm 時會有最好的表現。然而由於源極偏壓與汲極偏壓不同,對稱型的側壁結構不見得能得到元件最佳的表現,因此進行非對稱型結構設計,並求得汲極端側壁在 Linner,D = 3.75 nm、Hinner,D = 3.00 nm 具有最佳的開關比、次臨界擺幅及汲極引發位能障下降,作為本論文整體研究的最佳設計。 Conventional metal-oxide-semiconductor field-effect transistors (MOSFET) continue to scale with Moore's Law, resulting in reduced gate-to-channel controllability which in turn leads to short channel effects. In order to improve the gate-to-channel controllability and suppress the short channel effects, fin-field effect transistors (FinFET) have been developed and brought the substantial breakthrough for the semiconductor manufacturing technology. In order to further improve device performance and suppress short channel effects, the gate-all-around field-effect transistors (GAAFET) has superior device performance and gate-to-channel controllability than FinFET due to its maximum surface-to-volume ratio. And is considered to be the candidate structure for the next generation to replace FinFET. In this thesis, the GAAFETs are designed according to structure parameters for the 5-nm technology node for low-power applications and the underlap structure is used to suppress the leakage current. However, due to the underlap structure, the increase of the channel resistance will cause the on-state current to decrease rapidly and reduce the device performance. Therefore, it is necessary to make a spacer with a high dielectric constant (High-κ) material to increase the gate fringing field coupled to the underlap region to reduce the resistance. However, the High-κ spacer also results in a higher gate capacitance, which increases the intrinsic delay of device. Therefore, with the dual spacer structure design, the external spacer made of vacuum and the inner spacer made of HfO2 can simultaneously reduce the gate capacitance and further enhance the electrical performance of the device. After selecting the materials for the dual spacer structure, the length and height of the inner spacer are optimized, and the best performance is obtained when Linner = 3.75 nm and Hinner = 6.00 nm. However, since the source bias is different from the drain bias, so the asymmetric spacer design is analyzed, and the spacer of the drain is found at Linner,D = 3.75 nm and Hinner,D = 3.00 nm. The GAAFET with the asymmetric spacer design proposed in this thesis has the best on-off ratio, subthreshold swing and drain induced barrier lowering. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/21139 |
DOI: | 10.6342/NTU201904381 |
全文授權: | 未授權 |
顯示於系所單位: | 光電工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-108-1.pdf 目前未授權公開取用 | 19.73 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。