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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Li-Sheng Hsu | en |
dc.contributor.author | 許立昇 | zh_TW |
dc.date.accessioned | 2021-06-08T02:38:36Z | - |
dc.date.copyright | 2018-07-19 | |
dc.date.issued | 2018 | |
dc.date.submitted | 2018-07-16 | |
dc.identifier.citation | Bibliography
[1] Intel, “Intel Solid-State Drive DC S3500 Series Product Specification,” January 2015, https://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-dc-s3500-spec.pdf [2] T. Nabeshima, T. Sato, S. Yoshida, S. Chiba, K. Onda, “Analysis and design considerations of a buck converter with a hysteretic PWM controller,” in Proc. IEEE PESC, June 2004, vol. 2, pp. 1711–1716. [3] P. Luo, W. Deng, H. Li, S. Zhen, “A high energy efficiency PSM/PWM dual-mode for DC-DC converter in portable applications,” in Proc. IEEE ICCCAS, 2009, pp. 702–706. [4] T. Sato, T. Nabeshima, K. Nishijima, T. Nakano, “DC-DC Converters with a Novel Hysteretic PWM Controller,” in Proc. IEEE IECON, 2006, pp. 2729–2733. [5] J. H. Cheon, S. J. Kim, D. S. Lee and K. Y. Lee, 'Low-dropout regulator with low output peak voltage with soft-start added to bandgap reference output,' 2017 International SoC Design Conference (ISOCC), Seoul, Korea (South), 2017, pp. 210-211 [6] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic, 2001. [7] 梁適安,交換式電源供應器之理論與實務設計,二版,全華科技圖書,2008。 [8] 王信雄,開關轉換器:控制理論與設計實務,立錡科技股份有限公司,城邦印書館,2015。 [9] H. Deng, X. Duan, N. Sun, Y. Ma, A. Q. Huang, and D. Chen, “Monolithically Integrated Boost Converter Based on 0.5-μm CMOS Process,” IEEE J. Solid-State Circuits, vol. 20, no. 3, pp. 628–638, May 2005. [10] N. Dalarsson, 'The buck-boost DC/DC converter,' INTELEC - Twentieth International Telecommunications Energy Conference (Cat. No.98CH36263), San Francisco, CA, 1998, pp. 595-602. [11] B. Razavi, Design of Analog CMOS Integrated Circuit, Mcgraw-Hill Higher Education, 2001. [12] Jeongjin Roh, 'High-performance error amplifier for fast transient DC-DC converters,' in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 9, pp. 591-595, Sept. 2005. [13] M. Mulligan, B. Broach, T. Lee, “A 3-MHz low-voltage buck converter with improved light load efficiency,” in ISSCC Analog and Power Management Tech. Papers, pp. 528-529, 2007. [14] S. Kanemaru, T. Nabeshima, T. Nakano, “Transient response in a buck converter with bulk decoupling capacitors employing load current feedforward control,” in Proc. IEEE Power Electronics and Motion Control Conf., 2000, vol. 1, pp. 258–262. [15] R. Redl, B. P. Erisman, Z. Zansky, “Optimizing the load transient response of the buck converter,” in Proc. IEEE APEC, 1998, vol. 1, pp. 170–176. [16] Cheung Fai Lee and Philip K. T. Mok, “A Monolithic Current - Mode CMOS DC – DC Converter With On-Chip Current-Sensing Technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, January 2004. [17] T. T. Song, N. Huang, A. Ioinovici, “A family of zero-voltage and zero-current-switching (ZVZCS) three-level DC-DC converters with secondary-assisted regenerative passive snubber,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 2473–2481, Nov. 2005. [18] H. W. Huang, K. H. Chen, and S. Y. Kuo, “Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications,” IEEE J. Solid-State Circuits, vol.42, no.11, pp. 2451–2465, Nov. 2007. [19] Y. Zheng, H. Chen and K. N. Leung, 'A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, pp. 1167-1174, July 2012. [20] Y. H. Lee, S. C. Huang, S. W. Wang and K. H. Chen, 'Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 10, pp. 1781-1793, Oct. 2012. [21] T. J. Tseng, C. H. Wu and L. R. Chang-Chien, 'Fast transient voltage-mode buck regulator applying ramp signal with a variable DC-offset scheme,' in IET Power Electronics, vol. 5, no. 8, pp. 1408-1417, September 2012. [22] P. J. Liu, W. S. Ye, J. N. Tai, H. S. Chen, J. H. Chen and Y. J. E. Chen, 'A High-Efficiency CMOS DC-DC Converter With 9-μs Transient Recovery Time,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 3, pp. 575-583, March 2012. [23] S. H. Lee et al., '12.1 A 0.518mm2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS,' 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/20000 | - |
dc.description.abstract | 本論文闡述一個在負載改變下利用改良結構的轉導放大器之直流直流降壓轉換器,並透過TSMC 0.35μm 2P4M CMOS製程製作。在直流直流降壓轉換器的操作中,當負載突然改變時,輸出電壓會因為負載電流的大幅度變動而有短暫不穩定的狀況,若能縮短其回復時間,即能達到省電的目的並可以使後級電路更快速地進入工作階段。為了使電路同時兼顧快速響應及低功率消耗,本論文提出一種雙模式操作的直流直流降壓轉換器。當系統穩定時,轉導放大器之加速輔助電路不會啟動,使其維持在較低的靜態電流之操作模式,達到節省功率損耗的目的;然而,當偵測到負載電流改變時,轉導放大器上的加速輔助電路將會啟動並提高其轉導值及頻寬,得以產生大電流對補償電路充放電,使轉導放大器輸出之誤差放大訊號能快速反應。因此,後級的脈波寬度調變器即能迅速地產生適當的脈波寬度來驅動功率電晶體讓直流直流降壓轉換器的輸出電壓更快地回到穩定狀態,進而改善暫態響應。
本系統設定的輸出電流範圍為100mA至500mA,操作頻率則設定在1MHz,根據量測結果,經改良過後的直流直流降壓轉換器之暫態響應回復時間為4μs,表現比原本的轉導放大器架構改進4倍。 | zh_TW |
dc.description.abstract | Power management integrated circuits (PMICs) have been designed for low quiescent current and high-speed operation in these years. Since devices stay in stand-by mode most of the time, improving light-load efficiency is essential to extend their operation time. For the transient state, converter has to reduce recovery time to activate other circuits as soon as possible.
The dual operating modes control technique is presented to achieve fast-transient response for DC-DC buck converters in this thesis. The proposed operational transconductance amplifier (OTA) structure with auxiliary circuits, and it is used as error amplifier in the pulse width modulation (PWM) control circuit. First, boundaries of the steady state are defined as 3.28V and 3.32V, and the output voltage is 3.3V. In the steady state, the system operates with low quiescent current to reduce the power consumption. Without this range, the auxiliary circuits are applied to provide the additional current paths to improve output swing and bandwidth of the OTA. This method conduces to transient response by accelerating the output level shifting of the error amplifier. Then, pulse width modulator generates the proper signal to control power transistors. In this design, we consider both load transient response and high efficiency. The proposed DC-DC converter is fabricated using TSMC 0.35μm 2P4M CMOS technology. The chip area is 〖1.372×1.465 mm〗^2. The switching frequency is set at 1MHz. The load current range is from 100mA to 500mA. Measurement results demonstrate that the recovery time of the proposed structure are 4μs and 3μs for step-up and step-down load transient, respectively. Comparing with conventional one, we find that it takes only a quarter of the time to transit to the steady state. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T02:38:36Z (GMT). No. of bitstreams: 1 ntu-107-R04943164-1.pdf: 3051201 bytes, checksum: 906fd9d584524fdacd3a529fca051925 (MD5) Previous issue date: 2018 | en |
dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamental of DC-DC Converter 3 2.1 Voltage Regulator 3 2.1.1 Linear Regulator 3 2.1.2 Switching Regulator 5 2.2 DC-DC Buck Converter 8 2.2.1 Operation Mode 8 2.2.2 Boundary Condition and Estimation of Output Voltage Ripple 10 2.3 Performance Metrics 13 2.3.1 Efficiency 13 2.3.2 Regulation 16 2.3.3 Transient Response 17 Chapter 3 AC Analysis Using SIMPLIS 20 3.1 Specification of DC-DC Buck Converter 20 3.2 System Architecture 21 3.3 Behavior Simulation 23 3.3.1 Sub-circuit Behavior Model 23 3.3.2 Performance of Load Transient 26 3.3.3 AC simulation 28 Chapter 4 Circuit Implementation 30 4.1 Power Stage 31 4.2 OTA 33 4.2.1 Original OTA 34 4.2.2 Conventional OTA 35 4.2.3 Proposed OTA 36 4.3 Oscillator 40 4.4 Comparator 42 4.5 Driver 44 4.6 Simulation Result 46 Chapter 5 Experiment Results 50 5.1 Measurement Setup 50 5.2 Measurement Results 54 Chapter 6 Conclusion and Future Work 59 6.1 Conclusion 59 6.2 Future Work 59 Bibliography 60 | |
dc.language.iso | en | |
dc.title | 具加速機制之電壓模式降壓直流電壓轉換器 | zh_TW |
dc.title | A Fast Transient Voltage Mode DC-DC Buck Converter with Dual Operating Modes Control Technique | en |
dc.type | Thesis | |
dc.date.schoolyear | 106-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉宗德(Tsung-Te Liu),邱煌仁(Huang-Jen Chiu),林景源(Huang-Jen Chiu) | |
dc.subject.keyword | 直流直流降壓轉換器,暫態響應,轉導放大器, | zh_TW |
dc.subject.keyword | DC-DC buck converter,Transient response,OTA, | en |
dc.relation.page | 62 | |
dc.identifier.doi | 10.6342/NTU201801361 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2018-07-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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