一個具能量提升功能的13.56MHz電流模式無線功率接收器

Abstract

隨著物聯網、穿戴式裝置與可植入性醫療元件的發展，無線功率傳輸受到相當大的關注。在相關應用中，發射端所送出的能量，經由線圈/天線傳遞後，可在無線裝置上產生交流電壓。在傳統無線功率傳輸系統中，會使用交流-直流轉換串接直流-直流轉換以產生精確的電壓來對電池充電。最近，電流模式無線功率接收器被提出。使用電感電流對電池充電，避免了整流與電壓調節。如此省去了直流-直流轉換，因此改善效率。這減少了晶片面積與外部元件。 本論文提出一個具能量投資功能的13.56MHz電流模式無線功率接收器。當系統處於充電模式，此電路並不同於既有文獻，將諧振電路內所有的能量對輸出電池作充電，反而，保留了部分能量貯存在共振電容上作為一個投資電壓。當系統結束充電開始諧振電路並且累積能量時，投資電壓提供了線圈初始電壓。這增加了從電動勢攫取能量的能力。此電路運用低頻率時脈的採樣並保持電路來採樣電壓，以及運用數位控制延遲電路來調整切換功率電晶體的時間。如此一來，操作電壓可提升到13.56MHz。避免控制電路中使用高頻寬電路，並且節省功率消耗。此電路實現於0.18微米CMOS製程，有效面積0.341平方毫米。當輸入功率達6mW，達到最高功率傳輸效率67.1%。

For the development of the Internet of Things (IoT), wearable devices, and implantable medical devices, the wireless power transmission is receiving significant attention. In these applications, the external power from a transmitter is transmitted by the coils / antennas, and an AC voltage will be received in a wireless device. In the traditional wireless power transfer systems, the AC-DC conversion systems followed by the DC-DC conversion systems are used to generate an accurate voltage to safely charge a battery. Recently, the current-mode wireless power receivers are presented. By charging the battery with inductor current, the current-mode wireless power systems avoid rectification and voltage regulation. Therefore, the DC-DC conversion systems are spared and the PCE is improved. Also, the chip area and the off-chip components are reduced. This thesis presents a 13.56MHz current-mode wireless power receiver with energy-investment capability. When the system is in the charging mode, this work does not charge the output battery with all the power in the LC tank as the state-of-the-art systems do, this work reserves a fraction of energy stored as an investing voltage in the resonate capacitor instead. The investing voltage gives an initial voltage of the coil when this work finishes charging and starts to accumulate energy. The investing voltage increases the ability to grab energy from electromotive force (EMF). This work employs sample and holds circuits (SAHs) with low-frequency clocks to sample voltage and digital controlled delay lines (DCDLs) to control the switching timing of the power MOS. By this way, the operation frequency can be raised to 13.56MHz. High bandwidth circuits are avoided in the control circuits and power is saved. This work is fabricated in a 0.18-µm CMOS process and the active area is 0.341mm2. It achieves a peak PCE of 67.1% when the input power is 6mW.