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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19089
Title: | 具有校正頻寬之全數位資料回復電路 An All-Digital Clock and Data Recovery Circuit with Bandwidth Calibration |
Authors: | Yu-Syuan Du 杜昱璇 |
Advisor: | 劉深淵(Shen-Iuan Liu) |
Keyword: | 全數位資料回復電路,資料回復電路,抖動傳遞頻寬, Digital clock and data recovery circuit,clock and data recovery circuit,jitter transfer bandwidth, |
Publication Year : | 2016 |
Degree: | 碩士 |
Abstract: | 這篇論文的主題為提出一個具有校正頻寬之9.5Gb/s全數位資料回復電路。此論文提出一種校正頻寬的機制,使得當輸入資料密度變動時頻寬固定。此全數位資料回復電路使用28奈米製程製做。晶片面積為0.065毫米平方。在電源1.05伏特下消耗的功率為33毫瓦。量測到的回復時脈方均根抖動為2.25ps。 This thesis describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) with bandwidth calibration for 9.5 gigabit/s operation. The proposed architecture achieves constant jitter transfer bandwidth independent of data transition density. This ADCDR is fabricated in 28-nm CMOS technology. Its active area is 0.065mm2 and the power is 33mW from a supply of 1.05 V. The integrated RMS jitter is 2.25ps for PRBS7. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/19089 |
DOI: | 10.6342/NTU201602687 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-105-1.pdf Restricted Access | 1.98 MB | Adobe PDF |
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