兩百億位元每秒可適性線性等化器與決策回授等化器之設計

Abstract

現今，為了減少輸入/輸出基板的面積及降低製作的成本，資料串列化傳輸的架構在有線資料傳輸系統中越受歡迎。然而，高速資料的傳輸頻寬卻受限於通道的特性，有限的通道頻寬會造成資料傳輸時明顯的符際干擾，同時也將使資料的錯誤率大為提高，有鑑於此，於有線通訊中加入資料等化的技巧顯得日益重要。此外，通道衰減的特性會隨通道材質及長度的不同而異，因此，可適性技術對於等化器在多數系統應用中是迫切需要的。 本論文中，接收端常見的等化器架構均被實際設計、分析、及驗證。第一個部分介紹一個兩百億位元每秒的線性等化器及其提出的可適性方法，實作於40奈米製程中，此可適性線性等化器可適當的補償小於18.3dB衰減的串列資料，其中，等化器係數收斂僅需2.68微秒，而實現可適性方法的邏輯電路其功率消耗也僅有4.9毫瓦。 第二部分則提出一個兩百億位元每秒的無限脈衝響應之決策回授等化器。為了提升使用功率的效益，電荷導向式邏輯電路被應用於此設計當中，此外，四分之一資料速率的架構，及許多電路合併的技巧也被應用於此。實現於40奈米製程，此等化器的功率效益可達到0.31毫瓦每十億位元每秒。

Nowadays, the SerDes (Serializer-to-Deserializer) topology is increasingly popular in the wireline communication systems for the reduced I/O pads and also the low fabrication cost. However, the aggregate bandwidth of the data traffic is strictly limited by the channel characteristics. The limited bandwidth of the channel will induce large inter-symbol interference (ISI), and also deteriorate the bit-error-rate (BER) performance. Thus, the equalization is more and more important in the wireline systems. Moreover, the channel attenuation greatly varies with materials and lengths, and hence the adaptation techniques for the equalizer are required in most applications. In this thesis, the most common equalizers in the receiver are designed, analyzed, and verified. The first part shows a 20Gbps linear equalizer with the proposed adaptation method. Fabricated in 40nm CMOS technology, this adaptive linear equalizer can well compensate the channel loss under 18.3dB attenuation. Only 2.68us is required for the adaptation procedure and 4.9mW is consumed by the adaptation logics. The second part presents a 20Gbps infinite impulse response decision feedback equalizer (IIR-DFE). To enhance the power efficiency of the IIR-DFE, the charge-steering logic (CSL) is utilized in this work. Besides, the quarter-rate topology and some circuit merging techniques are adopted. Fabricated in 40nm CMOS technology, the power efficiency of 0.31mW/Gbps can be obtained.