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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
dc.contributor.author | Kuan-Yu Chen | en |
dc.contributor.author | 陳冠宇 | zh_TW |
dc.date.accessioned | 2021-06-08T01:38:04Z | - |
dc.date.copyright | 2017-02-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-11-03 | |
dc.identifier.citation | [1] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058–2066, Sep. 2006.
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18865 | - |
dc.description.abstract | 現今,為了減少輸入/輸出基板的面積及降低製作的成本,資料串列化傳輸的架構在有線資料傳輸系統中越受歡迎。然而,高速資料的傳輸頻寬卻受限於通道的特性,有限的通道頻寬會造成資料傳輸時明顯的符際干擾,同時也將使資料的錯誤率大為提高,有鑑於此,於有線通訊中加入資料等化的技巧顯得日益重要。此外,通道衰減的特性會隨通道材質及長度的不同而異,因此,可適性技術對於等化器在多數系統應用中是迫切需要的。
本論文中,接收端常見的等化器架構均被實際設計、分析、及驗證。第一個部分介紹一個兩百億位元每秒的線性等化器及其提出的可適性方法,實作於40奈米製程中,此可適性線性等化器可適當的補償小於18.3dB衰減的串列資料,其中,等化器係數收斂僅需2.68微秒,而實現可適性方法的邏輯電路其功率消耗也僅有4.9毫瓦。 第二部分則提出一個兩百億位元每秒的無限脈衝響應之決策回授等化器。為了提升使用功率的效益,電荷導向式邏輯電路被應用於此設計當中,此外,四分之一資料速率的架構,及許多電路合併的技巧也被應用於此。實現於40奈米製程,此等化器的功率效益可達到0.31毫瓦每十億位元每秒。 | zh_TW |
dc.description.abstract | Nowadays, the SerDes (Serializer-to-Deserializer) topology is increasingly popular in the wireline communication systems for the reduced I/O pads and also the low fabrication cost. However, the aggregate bandwidth of the data traffic is strictly limited by the channel characteristics. The limited bandwidth of the channel will induce large inter-symbol interference (ISI), and also deteriorate the bit-error-rate (BER) performance. Thus, the equalization is more and more important in the wireline systems. Moreover, the channel attenuation greatly varies with materials and lengths, and hence the adaptation techniques for the equalizer are required in most applications.
In this thesis, the most common equalizers in the receiver are designed, analyzed, and verified. The first part shows a 20Gbps linear equalizer with the proposed adaptation method. Fabricated in 40nm CMOS technology, this adaptive linear equalizer can well compensate the channel loss under 18.3dB attenuation. Only 2.68us is required for the adaptation procedure and 4.9mW is consumed by the adaptation logics. The second part presents a 20Gbps infinite impulse response decision feedback equalizer (IIR-DFE). To enhance the power efficiency of the IIR-DFE, the charge-steering logic (CSL) is utilized in this work. Besides, the quarter-rate topology and some circuit merging techniques are adopted. Fabricated in 40nm CMOS technology, the power efficiency of 0.31mW/Gbps can be obtained. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T01:38:04Z (GMT). No. of bitstreams: 1 ntu-105-R02943011-1.pdf: 5680929 bytes, checksum: c9b0448d293550dbd682903069a26d8a (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | Chapter 1. Introduction 1
1.1 Overview 1 1.2 Wireline Communication 2 1.3 Equalization 3 1.3.1 Feedforward Equalizer (FFE) 3 1.3.2 Continuous Time Linear Equalizer (CTLE) 4 1.3.3 Decision Feedback Equalizer (DFE) 4 1.4 Thesis Organization 5 Chapter 2. A 20Gbps Adaptive Linear Equalizer Using a Fast-Converging Method 7 2.1 Motivation 8 2.2 Proposed Adaptation Method 10 2.3 Circuit Descriptions 12 2.3.1 Linear Equalizer 12 2.3.2 Comparator and Clock Generator 21 2.3.3 Digital Controller 22 2.3.4 Adaptation Time Analysis 24 2.4 Experimental Results 27 2.4.1 Measurement Setup 27 2.4.2 Experimental Results 29 2.5 Conclusion 34 Chapter 3. A Low-Power 20Gbps DFE with 1 Discrete Tap and 2 IIR Filters Feedback 35 3.1 Motivation 36 3.2 Circuit Descriptions 38 3.2.1 Slicer-merged Summer 39 3.2.2 Proposed MUX-merged IIR Filter 41 3.2.3 Others 42 3.3 Timing Analysis of Quarter-rate IIR-DFE 43 3.3.1 Race Condition of CSL-based DFE 43 3.3.2 Critical Path Delay Issue 45 3.4 Experimental Results 47 3.4.1 Measurement Setup 47 3.4.2 Experimental Results 48 3.5 Proposed adaptation method 53 3.5.1 Adaptation Method Descriptions 53 3.5.2 Circuit Descriptions 58 3.5.3 Simulation Results 62 3.6 Conclusion 65 Chapter 4. Conclusion and Future Work 67 4.1 Conclusion 67 4.2 Future Work 68 Bibliography 69 | |
dc.language.iso | en | |
dc.title | 兩百億位元每秒可適性線性等化器與決策回授等化器之設計 | zh_TW |
dc.title | Design of 20Gbps Adaptive Linear Equalizer and Decision Feedback Equalizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),陳巍仁(Wei-Zen Chen),梁哲夫(Che-Fu Liang) | |
dc.subject.keyword | 線性等化器,決策回授等化器,可適性等化器,低功耗,快速收斂, | zh_TW |
dc.subject.keyword | continuous time linear equalizer (CTLE),decision feedback equalizer (DFE),adaptive equalizer,low power,fast-converging, | en |
dc.relation.page | 74 | |
dc.identifier.doi | 10.6342/NTU201603689 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2016-11-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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