具功率放大器效能提升迴路、低雜訊放大器與收發開關之收發器前端共同設計

Abstract

一個5.2-GHz射頻全積體化前端電路，結合一個收發開關、一個低雜訊放大器、一個功率放大器於單一CMOS上。基於共同化設計技術，元件間適當重複利用減少信號不必要的衰減及晶片面積的浪費。利用90-nm CMOS製程，所提出的射頻收發前端在沒有額外元件下，於接收模式雜訊指數為3.2 dB，於傳送模式有+25.9 dBm的飽和工率輸出。此外，運用此收發前端共同化設計技巧加入一個PA效能提升迴路，使得deep class-AB功率放大器輸出功率1-dB壓縮點提升0.9 dB。

A 5.2-GHz fully-integrated RF front-end combining the design of a T/R switch, an LNA, and a PA is presented for single-chip solution on CMOS. Based on the concept of circuit co-design, components are properly reused in order to minimize signal losses and chip area. The proposed RF front-end requires no off-chip components while demonstrates an NF of 3.2 dB in the receive mode, and a saturated output power of +25.9 dBm in the transmit mode by using a standard 90-nm CMOS process. Furthermore, based on this design technique, a transceiver frontend co-design with PA performance enhancement feedback loop is pulled up from the deep class-AB region, which is increased the OP1dB by 0.9 dB.