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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18286Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 呂良鴻(Liang-Hung Lu) | |
| dc.contributor.author | Hung-Yu Tsai | en |
| dc.contributor.author | 蔡弘鈺 | zh_TW |
| dc.date.accessioned | 2021-06-08T00:58:03Z | - |
| dc.date.copyright | 2015-02-06 | |
| dc.date.issued | 2015 | |
| dc.date.submitted | 2015-02-03 | |
| dc.identifier.citation | [1] Y. Wang, H. Wang, C. Hull, and S. Ravid, “A transformer-based broadband front-end combo in standard CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1810-1819, Aug. 2012.
[2] M.-C. Yeh, Z.-M. Tsai, R.-C. Liu, K.-Y. Lin, Y.-T. Chang, H. Wang, 'Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance,' IEEE Trans. Microw. Theory Tech, vol. 54, no.1, pp. 31-39, Jan. 2006. [3] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997. [4] B. Razavi, RF Microelectronic. 2nd ed. Upper Saddle River, NJ: Pearson, 2012. [5] H. S. Ruiz, R. B. Perez, Linear CMOS RF Power Amplifiers, Springer, Springer Science+Business Media, 2014. [6] R. Chang et al., “A fully integrated RF front-end with independent RX/TX matching and +20dBm output power for WLAN applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 564-565. [7] M. Terrovitis et al., “A 1×1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization,” in Proc. of IEEE European Solid-State Circuit Conf., Sep. 2009, pp. 224-227. [8] C.-T. Fu, H. Lakdawala, S. S. Taylor, and K. Soumyanath, “A 2.5GHz 32nm 0.35mm2 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 56-57. [9] I. Bhatii, R. Roufoogaran, and J. Castaneda, “A fully integrated transformer-based front-end architecture for wireless transceivers,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 106-107. [10] S. Gross et al., “Dual-band CMOS transceiver with highly integrated front-end for 450Mb/s 802.11n systems,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2010, pp. 431-434. [11] C.-J. Chang et al., “A CMOS transceiver with internal PA and digital pre-distortion for WLAN 802.11a/b/g/n applications,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2010, pp. 435-438. [12] S. Abdollahi-Alibeik et al., “A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 170-171. [13] R. Kumar et al., “A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 328-329. [14] C.-W. P. Huang et al., “Novel silicon-on-insulator SP5T switch-LNA front-end IC enabling concurrent dual-band 256-QAM 802.11ac WLAN radio operations,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., June 2013, pp. 133-136. [15] T.-M. Chen et al., “A 2x2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2014, pp. 225-228. [16] Afsahi, A. Behzad, V. Magoon, L.E. Larson,'Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2x2 802.11n MIMO WLAN SoC,' IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 955-966, May. 2010. [17] N. Sornin, N.Massei, L. Perraud, C. Pinatel, 'A robust Cartesian feedback loop for a 802.11a/b/g CMOS transmitter,' in IEEE Radio Frequency Integrated Circuits Symp. Dig., Jun. 2004, pp. 145-148. [18] S. Kousai, K. Onizuka, T. Yamaguchi, Y. Kuriyama, and M. Nagaoka, “A 28.3 mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1 dBm WCDMA CMOS power amplifier,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2964-2973, Dec. 2012. [19] D. J. Comer and D. T. Comer, “Using the weak inversion region to optimize input stage design of CMOS op amps,” IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 51, no. 1, pp. 8–14, Jan. 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/18286 | - |
| dc.description.abstract | 一個5.2-GHz射頻全積體化前端電路，結合一個收發開關、一個低雜訊放大器、一個功率放大器於單一CMOS上。基於共同化設計技術，元件間適當重複利用減少信號不必要的衰減及晶片面積的浪費。利用90-nm CMOS製程，所提出的射頻收發前端在沒有額外元件下，於接收模式雜訊指數為3.2 dB，於傳送模式有+25.9 dBm的飽和工率輸出。此外，運用此收發前端共同化設計技巧加入一個PA效能提升迴路，使得deep class-AB功率放大器輸出功率1-dB壓縮點提升0.9 dB。 | zh_TW |
| dc.description.abstract | A 5.2-GHz fully-integrated RF front-end combining the design of a T/R switch, an LNA, and a PA is presented for single-chip solution on CMOS. Based on the concept of circuit co-design, components are properly reused in order to minimize signal losses and chip area. The proposed RF front-end requires no off-chip components while demonstrates an NF of 3.2 dB in the receive mode, and a saturated output power of +25.9 dBm in the transmit mode by using a standard 90-nm CMOS process. Furthermore, based on this design technique, a transceiver frontend co-design with PA performance enhancement feedback loop is pulled up from the deep class-AB region, which is increased the OP1dB by 0.9 dB. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-08T00:58:03Z (GMT). No. of bitstreams: 1 ntu-104-R01943026-1.pdf: 3342654 bytes, checksum: fea7ad9731bc6d0a4eb90bc870408a3d (MD5) Previous issue date: 2015 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii Abstract v Contents vii List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis organization 2 Chapter 2 Background 3 2.1 The low noise amplifier 3 2.1.1 Noise figure and sensitivity 4 2.1.2 Linearity 5 2.1.3 The inductive source degeneration LNA topology 6 2.2 The power amplifier 8 2.2.1 General considerations of power amplifier 8 2.2.2 The optimal impedance for the power amplifier design 10 2.2.3 The cascode topology of power amplifier with I/O device 11 2.3 The T/R switch 12 2.4 The concept of front-end circuits co-design 14 Chapter 3 A 5.2-GHz CMOS Transceiver Frontend by T/R switch, LNA, and PA Co-design 17 3.1 Introduction 18 3.2 The proposed system architecture 19 3.3 Circuit implementation 22 3.3.1 Co-design of LNA and T/R switch 22 3.3.2 Co-design of PA and T/R switch 26 3.4 Experimental Results 31 3.5 Conclusion 37 Chapter 4 Transceiver Frontend Co-design with PA Performance Enhancement Feedback Loop 39 4.1 Introduction 40 4.2 The proposed system architecture 42 4.3 Circuit implementation 45 4.3.1 Voltage leakage detection 45 4.3.2 The PA of envelope loop detector of linearization circuit 46 4.4 Experimental Results 49 4.5 Conclusion 55 Chapter 5 Conclusion 57 Reference 59 | |
| dc.language.iso | en | |
| dc.title | 具功率放大器效能提升迴路、低雜訊放大器與收發開關之收發器前端共同設計 | zh_TW |
| dc.title | Transceiver Frontend Co-design with PA Performance Enhancement Feedback Loop | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 103-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭建男(Chien-Nan Kuo),徐碩鴻(Shuo-Hung Hsu) | |
| dc.subject.keyword | 共同化設計,低雜訊放大器,功率放大器,收發開關,收發器前端,變壓器,線性化回授迴路, | zh_TW |
| dc.subject.keyword | Co-design,low-noise amplifier,power amplifier,T/R switch,transceiver front-end,transformer,linearization feedback loop, | en |
| dc.relation.page | 62 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2015-02-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-104-1.pdf Restricted Access | 3.26 MB | Adobe PDF |
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