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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17704
標題: | 應用於SATA-III且具有自我調變以Δ-Σ鎖相迴路為基底之6 GHz展頻時脈產生器 A Δ-Σ PLL-Based 6 GHz Spread Spectrum Clock Generator with Self-Calibration for SATA-III |
作者: | Wen-Yuan Chang 張文原 |
指導教授: | 陳中平(Chung-Ping Chen) |
關鍵字: | 電磁干擾,頻率調變,展頻時脈,展頻時脈產生器,鎖相迴路,自我調變,頻率合成器,除小數, delta-sigma modulator,sigma-delta modulator,EMI reduction,frequency modulation,SSCG,PLL,serdes,fractional-N,phase-locked loop,serializer,deserializer,Spread Spectrum Clock Generator,Self-Calibration,frequency synthesizer,SATA, |
出版年 : | 2013 |
學位: | 碩士 |
摘要: | 在這份研究中,採用台積電90奈米混和訊號製程,實現一個應用於SATA-III且具有自我調變以Δ-Σ鎖相迴路為基底的6 GHz展頻時脈產生器。
首先我們採用鎖相迴路來產生中心頻率為6 Ghz 的時脈訊號。為了能對抗製程、電壓和溫度的變異,我們設計12個操作頻帶的電壓控制震盪器,使其具有足夠大的頻率調控,以及低增益的優點;為了使鎖相迴路能自動的選擇其操作頻帶,採用一個負回授,具有自動偵測鎖定頻率的調變系統。在展頻時脈的設計方面,採用一個二階23位元Δ-Σ調變器來調變多模除數除頻器,使鎖相迴路具有展頻的功能。Δ-Σ調變器的輸入端採用一個頻率為31.9 KHz的三角波來調控鎖相迴路的展頻範圍。以上兩者皆採用標準單元的方式來實現。 在實驗結果方面,測得其向下展頻量為5000 ppm,亦即操作頻率為6 GHz至5.97 GHz;其電磁干擾(EMI)的功率衰減量為15.46 dB。在鎖相迴路操作模式下,測得其峰對峰值與均方根值抖動量分別為3.3403 ps和26.2 ps;在展頻時脈產生器操作模式下,測得其峰對峰值與均方根值抖動量分別為3.7843 ps和32.9 ps。此晶片的核心電路面積為0.085 mm2,當操作頻率為 6 GHz 的時候,其功率消耗為15 mW。 In this research, the design of a Δ-Σ PLL-based 6 GHz spread spectrum clock generator with self-calibration for SATA 3rd-generation was fabricated using TSMC 90 nm mixed-signal process. In order to generate a center frequency at 6 GHz, a phase-locked loop is used. To confront the process, voltage and temperature (PVT) variations, the voltage-controlled oscillator (VCO) is designed with twelve frequency bands that has the advantages of low VCO gain (Kvco) and high tuning range. A self-calibration system (SCS) is adopted to automatically select the correct band. Finally for spread-spectrum clocking, a second-order 23-bit delta sigma modulator (DSM) and a 31.9 KHz triangular-waveform generator are implemented under cell-based design flow. The measured power attenuation of electromagnetic interference (EMI) is 15.46 dB with a deviation of less than 0.5% (5000 ppm). Operating at the PLL-mode, the measured RMS jitter and peak-to-peak jitter are 3.3403 ps and 26.2 ps respectively. Operating at the SSCG-mode, the measured RMS jitter and peak-to-peak jitter are 3.7843 ps and 32.9 ps respectively. The core area is 0.085 mm2 and the core power consumption is 15 mW at 6 GHz. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17704 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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