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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Wen-Yuan Chang | en |
dc.contributor.author | 張文原 | zh_TW |
dc.date.accessioned | 2021-06-08T00:32:07Z | - |
dc.date.copyright | 2013-07-08 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-07-01 | |
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Chulwoo, 'A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS,' in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 360-362. [38] C. Kuo-Hsing, H. Cheng-Liang, and C. Chih-Hsien, 'A 0.77 ps RMS jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique,' Solid-State Circuits, IEEE Journal of, vol. 46, pp. 1198-1213, 2011. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17704 | - |
dc.description.abstract | 在這份研究中,採用台積電90奈米混和訊號製程,實現一個應用於SATA-III且具有自我調變以Δ-Σ鎖相迴路為基底的6 GHz展頻時脈產生器。
首先我們採用鎖相迴路來產生中心頻率為6 Ghz 的時脈訊號。為了能對抗製程、電壓和溫度的變異,我們設計12個操作頻帶的電壓控制震盪器,使其具有足夠大的頻率調控,以及低增益的優點;為了使鎖相迴路能自動的選擇其操作頻帶,採用一個負回授,具有自動偵測鎖定頻率的調變系統。在展頻時脈的設計方面,採用一個二階23位元Δ-Σ調變器來調變多模除數除頻器,使鎖相迴路具有展頻的功能。Δ-Σ調變器的輸入端採用一個頻率為31.9 KHz的三角波來調控鎖相迴路的展頻範圍。以上兩者皆採用標準單元的方式來實現。 在實驗結果方面,測得其向下展頻量為5000 ppm,亦即操作頻率為6 GHz至5.97 GHz;其電磁干擾(EMI)的功率衰減量為15.46 dB。在鎖相迴路操作模式下,測得其峰對峰值與均方根值抖動量分別為3.3403 ps和26.2 ps;在展頻時脈產生器操作模式下,測得其峰對峰值與均方根值抖動量分別為3.7843 ps和32.9 ps。此晶片的核心電路面積為0.085 mm2,當操作頻率為 6 GHz 的時候,其功率消耗為15 mW。 | zh_TW |
dc.description.abstract | In this research, the design of a Δ-Σ PLL-based 6 GHz spread spectrum clock generator with self-calibration for SATA 3rd-generation was fabricated using TSMC 90 nm mixed-signal process.
In order to generate a center frequency at 6 GHz, a phase-locked loop is used. To confront the process, voltage and temperature (PVT) variations, the voltage-controlled oscillator (VCO) is designed with twelve frequency bands that has the advantages of low VCO gain (Kvco) and high tuning range. A self-calibration system (SCS) is adopted to automatically select the correct band. Finally for spread-spectrum clocking, a second-order 23-bit delta sigma modulator (DSM) and a 31.9 KHz triangular-waveform generator are implemented under cell-based design flow. The measured power attenuation of electromagnetic interference (EMI) is 15.46 dB with a deviation of less than 0.5% (5000 ppm). Operating at the PLL-mode, the measured RMS jitter and peak-to-peak jitter are 3.3403 ps and 26.2 ps respectively. Operating at the SSCG-mode, the measured RMS jitter and peak-to-peak jitter are 3.7843 ps and 32.9 ps respectively. The core area is 0.085 mm2 and the core power consumption is 15 mW at 6 GHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:32:07Z (GMT). No. of bitstreams: 1 ntu-102-R99945026-1.pdf: 3787854 bytes, checksum: 4707af1c94660bf59adc2b5725ed458f (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 誌謝 I
摘要 III Abstract V Table of Contents VII List of Figures XIII List of Tables XXIII Chapter 1 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 1.3 Bibliography 3 Chapter 2 5 Spread Spectrum Clock Generation Overview 5 2.1 EMI Reduction Techniques 5 2.1.1 Electromagnetic Shielding 5 2.1.2 Differential Clocking 6 2.1.3 Low-Voltage Differential Signaling 7 2.1.4 Pulse-Shaping Filter 8 2.1.5 Slew Rate Control 9 2.1.6 Staggered Outputs 9 2.1.7 Spread Spectrum Clocking 10 2.2 Fundamentals of the Spread Spectrum Modulation 10 2.3 Different Types of the SSCG Modulation 14 2.3.1 Input Modulation 14 2.3.2 Control Voltage of the Oscillator Modulation 15 2.3.3 Output Phase Interpolation Modulation 16 2.3.4 Divider Feedback Loop Modulation 17 2.4 Δ-Σ Modulator 17 2.4.1 Accumulator 17 2.4.2 First-Order Δ-Σ Modulator 18 2.4.3 Second-Order Δ-Σ Modulator 21 2.4.4 Third-Order Δ-Σ Modulator 23 2.5 Modulation Profiles 25 2.5.1 Triangular Modulation Profile 26 2.5.2 Sinusoidal Modulation Profile 27 2.5.3 Hershey-Kiss Modulation Profile 28 2.5.4 Cubic Modulation Profile 29 2.6 Bibliography 30 Chapter 3 33 The Basics of Phase-Locked Loop 33 3.1 Phase-Locked Loop (PLL) Fundamentals 33 3.1.1 Phase-Frequency Detector (PFD) 34 3.1.2 Charge Pump (CP) 38 3.1.3 Voltage-Controlled Oscillator (VCO) 40 3.1.4 Loop Filter 41 3.2 High-Order Charge Pump PLL Analysis 44 3.2.1 Second-Order PLL 44 3.2.2 Third-Order PLL 46 3.2.3 Fourth-Order PLL 50 3.3 Phase Noise Performance Analysis 54 3.3.1 Control-Line Noise 54 3.3.2 Circuit Noise 56 3.3.3 Transfer Function of the Reference Noise 58 3.3.4 Transfer Function of the VCO Noise 60 3.4 Bibliography 62 Chapter 4 65 A Δ-Σ PLL-Based 6 GHz Spread Spectrum Clock Generator with Self-Calibration 65 4.1 System Architecture and Circuits 66 4.1.1 Second-Order Δ-Σ Modulator 67 4.1.2 Triangular Waveform Generator 69 4.1.3 6 GHz SSCG System Behavioral Simulation 73 4.1.4 Multi-Mode Divider (MMD) 76 4.1.5 Voltage-Controlled Oscillator (VCO) 79 4.1.6 Digital-to-Analog Converter (DAC) 83 4.1.7 Self-Calibration System (SCS) 84 4.1.8 Finite-State Machine (FSM) 86 4.1.9 N-Type Comparator 89 4.1.10 P-Type Comparator 91 4.1.11 Phase-Frequency Detector (PFD) 92 4.1.12 Charge Pump (CP) 94 4.1.13 Differential-to-Single Converter (DSC) 98 4.2 6 GHz SSCG System Simulation 99 4.2.1 6 GHz PLL-Mode Simulation Results 100 4.2.2 Mixed-Signal Co-Simulation Results 105 4.3 Bibliography 107 Chapter 5 111 Layout and Experimental Results 111 5.1 IC Layout 111 5.2 Printed Circuit Board (PCB) 113 5.2.1 Signal Descriptions 114 5.2.2 Measurement Setup Environment 115 5.3 Experimental Results 116 5.3.1 Spectrum Measurement of the PLL-mode 116 5.3.2 Phase Noise Measurement of the PLL-mode 117 5.3.3 Jitter Measurement of the PLL-mode 118 5.3.4 Spectrum Comparison Between the PLL-Mode and the SSCG-Mode 119 5.3.5 Jitter Measurement of the SSCG-mode 120 5.3.6 Vctrl Measurement of the SSCG-mode 121 5.4 Performance Summary and Comparison 123 5.4.1 Die Photo 123 5.4.2 Performance Summary 124 5.4.3 Performance Comparison with Conventional Works 125 5.5 Bibliography 125 Chapter 6 127 Conclusion 127 | |
dc.language.iso | en | |
dc.title | 應用於SATA-III且具有自我調變以Δ-Σ鎖相迴路為基底之6 GHz展頻時脈產生器 | zh_TW |
dc.title | A Δ-Σ PLL-Based 6 GHz Spread Spectrum Clock Generator with Self-Calibration for SATA-III | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),李泰成(Tai-Cheng Lee),張順志(Soon-Jyh Chang) | |
dc.subject.keyword | 電磁干擾,頻率調變,展頻時脈,展頻時脈產生器,鎖相迴路,自我調變,頻率合成器,除小數, | zh_TW |
dc.subject.keyword | delta-sigma modulator,sigma-delta modulator,EMI reduction,frequency modulation,SSCG,PLL,serdes,fractional-N,phase-locked loop,serializer,deserializer,Spread Spectrum Clock Generator,Self-Calibration,frequency synthesizer,SATA, | en |
dc.relation.page | 129 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-07-01 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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