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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭正邦 | |
dc.contributor.author | Ji-Yong Lin | en |
dc.contributor.author | 林基永 | zh_TW |
dc.date.accessioned | 2021-06-08T00:25:45Z | - |
dc.date.copyright | 2013-07-18 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-07-15 | |
dc.identifier.citation | [1] J.B. Kuo, J. Lou, Low-Voltage CMOS VLSI Circuits, Wiley, New York, 1999.
[2] G.E. Moore, 'Progress in digital integrated electronics,' International Electron Devices Meeting, vol.21, pp.11-13, 1975. [3] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2011 Edition, 2011, http://www.itrs.net/ [4] N.S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, V. Narayanan, “Leakage current: Moore's law meets static power,” Computer , vol.36, no.12, pp. 68-75, Dec. 2003. [5] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2002 Update, 2002, http://www.itrs.net/ [6] A. Bellaouar, M.I. Elmasry, Low-Power Digital VLSI Design:Circuits and System, Kluwer, 1996. [7] J. Kao, S. Narendra, A. Chandrakasan, “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns,” Design Automation Conference, pp.495-500, June 1998. [8] K. Usami, N. Kawabe, M. Koizumi, K. Seta, T. Furusawa, “Automated selective multi-threshold design for ultra-low standby applications,” International Symposium on Low Power Electronics and Design, pp.202-206, 2002. [9] R.X. Gu, M.I. Elmasry, “Power dissipation analysis and optimization of deep submicron CMOS digital circuits,” IEEE Journal of Solid-State Circuits, vol.31, no.5, pp.707-713, May 1996. [10] Liqiong Wei, Zhanping Chen, M. Johnson, K. Roy, V. De, “Design and optimization of low voltage high performance dual threshold CMOS circuits,” Design Automation Conference, pp.489-494, June 1998. [11] B. Chung, J.B. Kuo, “Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology,” IEEE International Symposium on Circuits and Systems, pp. 21-24, May 2006. [12] H. X. F. Huang, S. R. S. Shen, J. B. Kuo, “Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique,” International Workshop on Power And Timing Modeling, Optimization and Simulation, LNCS 6951, pp. 143–151, 2011. [13] Synopsys, PrimeTime Fundamentals User Guide, Version C-2009.06, June 2009. [14] Synopsys, PrimeTime PX User Guide, Version C-2009.06, June 2009. [15] Synopsys, Using Tcl With Synopsys Tools, Version B-2008.09, Sept. 2008. [16] Liqiong Wei, Zhanping Chen, K. Roy, Yibin Ye, V. De, “Mixed-Vth (MVT) CMOS circuit design methodology for low power applications,” Design Automation Conference, pp.430-435, 1999. [17] S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, D. Blaauw, “Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing,” Design Automation Conference, pp. 436-441, 1999. [18] F. Sill, F. Grassert, and D. Timmermann. “Total leakage power optimization with improved mixed gates,” 18th Symposium on Integrated Circuits and System Design, pp. 154-159, Sept. 2005. [19] F. Sill, J. You, and D. Timmermann. “Design of mixed gates for leakage reduction,” 17th ACM Great Lakes symposium on VLSI, pp. 263-268, 2007. [20] C.S. Nagarajan, Lin Yuan, Gang Qu, B.G. Stamps, “Leakage optimization using transistor-level dual threshold voltage cell library,” International Symposium on Quality Electronic Design, pp. 62-67, March 2009. [21] P. Gupta, A.B. Kahng, P. Sharma, “A practical transistor-level dual threshold voltage assignment methodology,” International Symposium on Quality Electronic Design, pp. 421-426, March 2005. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/17619 | - |
dc.description.abstract | 本篇論文提出了使用混合臨界電壓單元,來優化低電壓低功率電路的功率消耗的方法。首先在第二章中提出了使用混合臨界電壓單元,為低功率電路設計的功率消耗優化方法(PCOM)。透過以unbalanced timing arc做為混合臨界電壓單元變體的選取標準,並且採用一個以sensitivity為分配單元的基準的單元分配演算法,來將混合臨界電壓單元應用在電路優化流程中,PCOM提供了一個使用90奈米CMOS技術和1V供應電壓,包含3811個單元的16-bit乘法器電路,在最快的延遲時間限制條件下,比起以全部使用LVT單元的同樣電路,有45.36%的功率下降。然後在第三章中,提出了考慮關鍵路徑的電路功率消耗優化方法(CPAPCOM)。利用關鍵路徑權重的sensitivity做為單元分配演算法中分配單元為LVT、HVT、或MVT的基準,使CPAPCOM提供相同的16 bit乘法器電路,在最快的延遲時間限制條件下,比起以全部使用LVT單元的同樣電路,有44.90%的功率下降。 | zh_TW |
dc.description.abstract | This thesis reports a power consumption optimization methodology using mixed-threshold-voltage cells for low-voltage low-power designs. In Chapter 2, a power consumption optimization methodology (PCOM) using mixed-VTH (MVT) cells with for low-power designs has been presented. Via selecting MVT cell variant selection according to the “unbalanced timing arc” criteria and adopting a sensitivity-based cell assignment algorithm to integrate MVT cells out of HVT/LVT/MVT pools for the circuit optimization flow, the PCOM could provide a design as indicated in a 16-bit multiplier with 3811 cells, using a 90nm CMOS technology at 1V -under the tightest delay constraint a 45.36% reduction in power consumption as compared to the one using all-LVT cells. Then in Chapter 3, a critical-path aware power consumption optimization methodology (CPAPCOM) using mixed-VTH cells for low-power SOC designs has been presented. Using the critical-path weighted sensitivity as an index for assigning each cell to LVT, HVT or MVT cell, the CPAPCOM provides an effective power saving for a low-voltage/low-power SOC design, as indicated in the same 16-bit multiplier with a 44.90% reduction in power consumption as compared to the circuit using all-LVT cells. | en |
dc.description.provenance | Made available in DSpace on 2021-06-08T00:25:45Z (GMT). No. of bitstreams: 1 ntu-102-R00943092-1.pdf: 5212308 bytes, checksum: e280e1b350fe520430c4fafbf373dd96 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 誌謝 ii
中文摘要 iii Abstract iv 目錄 v 圖目錄 vii 表目錄 ix Chapter 1 導論 Introduction 1 1.1. 互補式矽金氧半超大型積體電路發展的趨勢(CMOS VLSI Trends) 1 1.2. 多重臨界電壓互補式矽金氧半單元技術(Multi-threshold CMOS Technology) 5 1.3. 數位電路設計流程(Digital Circuit Design Flow) 8 1.4. 論文架構 (Thesis Organization) 11 Chapter 2 混合臨界電壓電路功率消耗優化方法 Mixed-Threshold-Voltage (MVT) Power Consumption Optimization Methodology (PCOM) 12 2.1. 混合臨界電壓單元技術(Mixed-Vth Technique) 12 2.2. 混合臨界電壓單元變體的選取標準(MVT Cell Selection Criterion) 14 2.3. 單元分配演算法(Cell Assignment Algorithm) 20 2.4. 分析工具(Analysis Tool) 26 2.5. 實驗結果(Experimental Results) 29 Chapter 3 考慮關鍵路徑的電路功率消耗優化方法 Critical Path Aware Power Consumption Optimization Methodology (CPAPCOM) 40 3.1. 單元分配演算法(Cell Assignment Algorithm) 40 3.2. 實驗結果(Experimental Results) 46 Chapter 4 結論與未來方向 Conclusions & Future Work 52 參考文獻 53 | |
dc.language.iso | zh-TW | |
dc.title | 使用混合臨界電壓元件應用於低電壓低功率電路之功率消耗優化方法 | zh_TW |
dc.title | Power Consumption Optimization Methodology Using Mixed Threshold Voltage Cells for Low-Voltage Low-Power Designs | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳正雄,林吉聰,林浩雄,呂學士 | |
dc.subject.keyword | 低功率,電路優化,設計方法,雙重臨界電壓,混合臨界電壓, | zh_TW |
dc.subject.keyword | low power,circuit optimization,design methodology,dual threshold,MTCMOS,mixed threshold voltage,MVT, | en |
dc.relation.page | 55 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2013-07-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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