使用混合臨界電壓元件應用於低電壓低功率電路之功率消耗優化方法

Abstract

本篇論文提出了使用混合臨界電壓單元，來優化低電壓低功率電路的功率消耗的方法。首先在第二章中提出了使用混合臨界電壓單元，為低功率電路設計的功率消耗優化方法(PCOM)。透過以unbalanced timing arc做為混合臨界電壓單元變體的選取標準，並且採用一個以sensitivity為分配單元的基準的單元分配演算法，來將混合臨界電壓單元應用在電路優化流程中，PCOM提供了一個使用90奈米CMOS技術和1V供應電壓，包含3811個單元的16-bit乘法器電路，在最快的延遲時間限制條件下，比起以全部使用LVT單元的同樣電路，有45.36%的功率下降。然後在第三章中，提出了考慮關鍵路徑的電路功率消耗優化方法(CPAPCOM)。利用關鍵路徑權重的sensitivity做為單元分配演算法中分配單元為LVT、HVT、或MVT的基準，使CPAPCOM提供相同的16 bit乘法器電路，在最快的延遲時間限制條件下，比起以全部使用LVT單元的同樣電路，有44.90%的功率下降。

This thesis reports a power consumption optimization methodology using mixed-threshold-voltage cells for low-voltage low-power designs. In Chapter 2, a power consumption optimization methodology (PCOM) using mixed-VTH (MVT) cells with for low-power designs has been presented. Via selecting MVT cell variant selection according to the “unbalanced timing arc” criteria and adopting a sensitivity-based cell assignment algorithm to integrate MVT cells out of HVT/LVT/MVT pools for the circuit optimization flow, the PCOM could provide a design as indicated in a 16-bit multiplier with 3811 cells, using a 90nm CMOS technology at 1V -under the tightest delay constraint a 45.36% reduction in power consumption as compared to the one using all-LVT cells. Then in Chapter 3, a critical-path aware power consumption optimization methodology (CPAPCOM) using mixed-VTH cells for low-power SOC designs has been presented. Using the critical-path weighted sensitivity as an index for assigning each cell to LVT, HVT or MVT cell, the CPAPCOM provides an effective power saving for a low-voltage/low-power SOC design, as indicated in the same 16-bit multiplier with a 44.90% reduction in power consumption as compared to the circuit using all-LVT cells.