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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15942
Title: 使用90奈米CMOS之多標準全球衛星導航系統接收機前端電路
A 90-nm CMOS Multi-standard GNSS Receiver Front-end
Authors: Chi-Wei Cheng
鄭治葳
Advisor: 陳怡然(Yi-Jan Chen)
Keyword: 全球衛星導航,接收機,鏡相消除,低中頻,多相位濾波器,
GNSS,receiver,image reject,low-IF,polyphase filter,
Publication Year : 2012
Degree: 碩士
Abstract: 本論文提出一個應用在多標準全球衛星導航(GNSS)接收機前端電路架構用來同時接收L1頻段的衛星導航訊號,包含美國的GPS、俄國的GLONASS、以及歐盟的Galileo。由於未來全球衛星導航系統將不是只有一種規格,而且各個規格有各自的軌道安排考量,預期同時接收多種規格的衛星導航訊號並交由後端數位訊號處理(DSP)綜合定位將會成為未來的趨勢。根據鏡像消除接收機的原理,利用一個頻率位於1588.57 MHz的本地震盪(LO)訊號,將位於1575.42 MHz的GPS及Galileo訊號和位於1597.5515 MHz 到 1605.886 MHz的GLOANSS訊號互相視為一組鏡像訊號,由於利用I/Q相位降頻時會讓本地震盪頻率兩端的射頻(RF)訊號擁有不同的訊號相位關係,透過多相位濾波器便可選擇出想要的頻率訊號,並且在輸出端被區分開來。不同於現行的接收機架構,此架構只利用一組接收機前端電路,如此可以節省晶片製作上的成本,並且有效的降低功率消耗。
我們採用了TSMC 90-nm CMOS製程設計並實現了一個全積體化的接收機電路,包括了低雜訊放大器(LNA)、 被動式混波器(Passive Mixer)、多相位濾波器(Polyphase Filter)、以及一個頻率合成器(Frequency Synthesizer),此電路為低中頻的架構,輸出頻率分別為GPS/Galileo的13.15 MHz和GLONASS的8.9815 MHz到17.316 MHz,並且提供20.5dB的鏡像消除,而在1V的電源供應器之下,功率消耗為15.79 mW、晶片面積為1.536 mm2
This thesis introduces a multi-standard receiver architecture aiming to simultaneously receive the L1 band Global Navigation Satellite System (GNSS) signals including GPS, GLONASS and Galileo. These multi-standard signals can be computed by the back-end DSP to provide a more robust navigation when GLONASS and Galileo become fully operational in the near future. Based on the principle of image-reject receiver with a LO frequency at 1588.57 MHz, the signals of GPS/Galileo at 1575.42 MHz and GLONASS at 1597.5515 MHz to 1605.886 MHz can be viewed as a pair of mirrored signals. From the differences in the phase relationship caused by I/Q down-converting signals in the double-side of LO frequency, we can select the desired output signal by a polyphase filter. This is the part that makes it different from the other multi-standard receiver architecture. Our approach receives three GNSS signals simultaneously with only one receiver chain. Therefore, this architecture provides the benefits of lowering the cost of chip manufacturing and increasing the power efficiency.
For the fabrication, we use TSMC 90-nm CMOS process to design and implement a fully integrated receiver circuit, including a low noise amplifier (LNA), passive mixers, polyphase filters, and a frequency synthesizer. This receiver is based on a low-IF architecture, and the output frequencies are 13.15 MHz for GPS/Galileo and 8.9815 MHz to 17.316 MHz for GLONASS respectively with a 20.14/20.5 dB image reject ratio. The power consumption is 15.79 mW with a 1-V power supply, and the die area is 1.536 mm2.
URI: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15942
Fulltext Rights: 未授權
Appears in Collections:電子工程學研究所

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