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Title: | 應用於多通道串接式通訊之鎖相迴路與可適性收發機 Phase-Locked Loop and Adaptive Transceiver for Multi-Channel Serial-Link Application |
Authors: | Shih-Yuan Kao 高世源 |
Advisor: | 劉深淵 |
Keyword: | 鎖相迴路,可適性傳送機,可適性接收機,多通道通訊,串接式通訊, phase-locked loop,adaptive transmitter,adaptive receiver,multi-channel application,serial-link application, |
Publication Year : | 2012 |
Degree: | 博士 |
Abstract: | 在串列連結應用中,當資料傳輸率達到每秒可傳送數億位元時,由於有限的頻寬使通道損耗變得嚴重。由通道的集膚效應和介電損失所引起的符際干擾會使收到資料的時間抖動變差,並惡化位元錯誤率。 為了增加資料頻寬,在多通道通訊系統中採用了平行介面傳輸,但產生的遠端干擾也會使時間抖動變差。此外,供應電壓雜訊會干擾對雜訊靈敏的類比電路並使其效能變差。
在本論文中,主要有五個部份。 在第二章中,在0.18微米CMOS製程下,實現一個1.5GHz的鎖相迴路,並具有壓抑供應電壓靈敏度的數位校正技巧。供應電壓雜訊模型的帶通特性亦被分析。在第三章中,在0.13微米CMOS製程下,實現一個1.62/2.7-Gb/s具有預先增強的可適性傳送機。其使用傳遞時間偵測器去量測傳遞時間並且調整閥係數。 在第四章中,在65奈米CMOS製程下,實現一個20-Gb/s 具有預先增強的可適性傳送機。其使用時間對數位轉化器去量測傳遞時間並且調整閥係數。在沒有使用回溯通道或共同合作的接收機情況下,此傳送機可達到低功率。在第五章中,在65奈米CMOS製程下,實現一個7.5-Gb/s具有可適性遠端干擾消除和前饋式等化器的傳送機。其使用責任週期偵測器去量測責任週期變化量並且調整干擾消除器的可適性係數。在第六章中,在40奈米CMOS製程下,實現一個10-Gb/s同時具有可適性干擾消除器和決策回授等化器的接收機。藉由使用雙迴路功率偵測技巧去數位校正兩者的閥係數。 As the data rate rises up to multi-gigabits per second in serial-link applications, the channel loss becomes severe due to the limited bandwidth. The inter-symbol interference (ISI) caused by skin effect and dielectric loss of the channel may degrade the timing jitter of received data and worsen the bit error rate (BER). To enhance the data bandwidth, the parallel interface is adopted in multi-channel communication. The far-end crosstalk (FEXT) may also degrade the timing jitter. Besides, the power supply noise may interfere with the noise-sensitive analog circuits to degrade the performance. In this dissertation, there are mainly five parts. In chapter 2, a digitally-calibrated technique to suppress the supply voltage sensitivity of a 1.5GHz phase-locked loop (PLL) is realized in a 0.18-μm CMOS technology. The band-pass characteristic for the supply noise model is also analyzed. In chapter 3, a 1.62/2.7-Gb/s adaptive transmitter with pre-emphasis is realized in a 0.13-μm CMOS technology. The propagation-time detector is used to measure the propagation time and adjust the tap coefficients. In chapter 4, a 20-Gb/s adaptive transmitter with pre-emphasis is realized in a 65-nm CMOS process. The time-to-digital converter is used to measure the propagation time and adjust the tap coefficients. This transmitter has a low power without the back channels or the collaborating receiver. In chapter 5, a 7.5-Gb/s transmitter with adaptive FEXT cancellation and a feed-forward equalizer is realized in a 65-nm CMOS process. The duty cycle detector is used to measure the duty cycle variation and adjust the adaptation coefficient of a crosstalk canceller. In chapter 6, a 10-Gb/s receiver with simultaneously adaptive crosstalk canceller and decision-feedback equalizer is realized in a 40-nm CMOS technology. The tap coefficients of both are digitally calibrated by using the dual-loop power detection. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15904 |
Fulltext Rights: | 未授權 |
Appears in Collections: | 電子工程學研究所 |
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ntu-101-1.pdf Restricted Access | 13.42 MB | Adobe PDF |
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