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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104856| 標題: | 應用於無線區域網路之瓦特級 CMOS 功率放大器與行動通訊 FR3/FR2 砷化鎵功率放大器晶片/模組之研製 Development of Watt-Level CMOS Power Amplifiers for WLAN and GaAs FR3/FR2 Power Amplifier IC/Module for Mobile Communications |
| 作者: | 詹淮安 Huai-An Chan |
| 指導教授: | 林坤佑 Kun-You Lin |
| 關鍵字: | 功率放大器; CMOS; GaAs pHEMT; 寬頻; 功率合成; 毫米波模組 power amplifier; CMOS; GaAs pHEMT; broadband; power combining; millimeter-wave module |
| 出版年 : | 2026 |
| 學位: | 碩士 |
| 摘要: | 此論文分為三個主要部分,分別探討應用於無線區域網路之 4.5–7.5 GHz 瓦特級 CMOS 功率放大器、應用於 FR3 相關微波通訊之 10–15 GHz GaAs pHEMT 寬頻高功率放大器,以及應用於 FR2 毫米波通訊之 28 GHz Ka-band GaAs 功率放大器模組。研究內容涵蓋功率放大器晶片設計、寬頻匹配網路、穩定度分析、被動結構損耗、功率合成及散熱設計。
第一部分介紹使用 90-nm CMOS 製程實現之 4.5–7.5 GHz 寬頻功率放大器。此電路採用兩級全差動架構,包含共源極驅動級與疊接式功率級,並於兩級放大器中加入交叉耦合中和電容,以降低電晶體閘極與汲極間寄生電容所造成之回授效應。輸入、級間及輸出匹配網路皆採用磁耦合共振器變壓器,以實現寬頻阻抗轉換及差動功率合成。量測結果顯示,此功率放大器之最大小訊號增益為 28.7 dB,飽和輸出功率為 29.3 dBm,輸出 1-dB 壓縮點為 24.5 dBm,峰值功率附加效率為 24.3%,整體晶片面積為 0.88 mm²。 第二部分介紹使用 0.15-μm GaAs pHEMT 製程實現之 10–15 GHz 寬頻高功率放大器。此電路採用兩級共源極架構,設計中使用寬頻輸入、級間與輸出匹配網路,並加入奇模穩定電阻及 RC 穩定網路,以提升多指電晶體與功率合成路徑之穩定度。量測結果顯示,在 10–15 GHz 頻段內,小訊號增益為 19.3–22.8 dB,飽和輸出功率為 31.85–33.09 dBm,輸出 1-dB 壓縮點為 30.28–32.55 dBm,功率附加效率為 35.75%–37.86%,整體晶片面積為 4.47 mm²。 第三部分介紹 28 GHz Ka-band GaAs 功率放大器模組之設計與量測。本研究完成 PCB 被動結構、單一 PA 模組及兩路功率合成模組之實作與特性分析,並分別使用 Wilkinson power divider/combiner、branch-line coupler 及 commercial divider/combiner module 實現三種 two-way power-combining PA module。量測結果顯示,三種模組之飽和輸出功率分別為 30.2、31.3 及 32.2 dBm,對應增益分別為 16.1、30.4 及 33.1 dB。此外,透過 Ansys Icepak 熱模擬與紅外線熱像量測,驗證銅製散熱結構可有效改善功率放大器模組之散熱能力。 This thesis consists of three main parts: a 4.5–7.5 GHz watt-level CMOS power amplifier for wireless local area network applications, a 10–15 GHz broadband GaAs pHEMT high-power amplifier for FR3-related microwave communication applications, and a 28 GHz Ka-band GaAs power amplifier module for FR2 millimeter-wave communication applications. The research covers power amplifier IC design, broadband matching networks, stability analysis, passive-structure loss characterization, power combining, and thermal design. The first part presents a 4.5–7.5 GHz broadband power amplifier implemented in a 90-nm CMOS technology. The proposed PA adopts a two-stage fully differential architecture consisting of a common-source driver stage and a cascode power stage. Cross-coupled neutralization capacitors are incorporated into both stages to reduce the feedback caused by the parasitic gate-to-drain capacitance of the transistors. Magnetically coupled resonator transformers are employed in the input, interstage, and output matching networks to achieve broadband impedance transformation and differential power combining. The measurement results show that the PA achieves a maximum small-signal gain of 28.7 dB, a saturated output power of 29.3 dBm, an output 1-dB compression point of 24.5 dBm, and a peak power-added efficiency of 24.3%. The total chip area is 0.88 mm². The second part presents a 10–15 GHz broadband high-power amplifier implemented in a 0.15-μm GaAs pHEMT technology. The proposed PA adopts a two-stage common-source architecture with broadband input, interstage, and output matching networks. Odd-mode stabilization resistors and RC stabilization networks are also incorporated to improve the stability of the multi-finger transistors and power-combining paths. Across the 10–15 GHz operating band, the measured small-signal gain ranges from 19.3 to 22.8 dB, the saturated output power ranges from 31.85 to 33.09 dBm, the output 1-dB compression point ranges from 30.28 to 32.55 dBm, and the power-added efficiency ranges from 35.75% to 37.86%. The total chip area is 4.47 mm². The third part presents the design and measurement of a 28 GHz Ka-band GaAs power amplifier module. PCB passive structures, unit PA modules, and two-way power-combining PA modules are implemented and characterized. Three two-way power-combining PA modules are realized using a Wilkinson power divider/combiner, a branch-line coupler, and commercial divider/combiner modules. The measured saturated output powers of the three modules are 30.2, 31.3, and 32.2 dBm, respectively, with corresponding gains of 16.1, 30.4, and 33.1 dB. In addition, thermal simulation using Ansys Icepak and infrared thermal imaging measurements verify that the proposed copper heat-spreading structure effectively improves the thermal performance of the PA module. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104856 |
| DOI: | 10.6342/NTU202604184 |
| 全文授權: | 同意授權(限校園內公開) |
| 電子全文公開日期: | 2029-07-31 |
| 顯示於系所單位: | 電信工程學研究所 |
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