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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電信工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104856
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor林坤佑zh_TW
dc.contributor.advisorKun-You Linen
dc.contributor.author詹淮安zh_TW
dc.contributor.authorHuai-An Chanen
dc.date.accessioned2026-09-02T16:37:02Z-
dc.date.available2026-09-03-
dc.date.copyright2026-09-02-
dc.date.issued2026-
dc.date.submitted2026-08-11 18:07:24-
dc.identifier.citation[1] J.-H. Tsai, “A 5.3-GHz 30.1-dBm fully integrated CMOS power amplifier with high-power built-in linearizer,” IEEE Microw. Wirel. Technol. Lett., vol. 33, no. 4, pp. 431–434, Apr. 2023.
[2] J.-K. Nai, Y.-H. Hsiao, Y. Wang, F. Chen, and H. Wang, “5-GHz transformer combined Class-F−1 power amplifier,” in Proc. IEEE Int. Symp. Radio-Frequency Integr. Technol. (RFIT), Taipei, Taiwan, 2016, pp. 1–3.
[3] A. Afsahi, A. Behzad, V. Magoon, and L. E. Larson, “Linearized dual-band power amplifiers with integrated baluns in 65 nm CMOS for a 2 × 2 802.11n MIMO WLAN SoC,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 955–966, May 2010.
[4] H. Solar, R. Berenguer, I. Adin, U. Alvarado, and I. Cendoya, “A fully integrated 26.5-dBm CMOS power amplifier for IEEE 802.11a WLAN standard with on-chip ‘power inductors’,” in Proc. IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, USA, 2006, pp. 1875–1878.
[5] M. Fathi, D. K. Su, and B. A. Wooley, “A 30.3-dBm 1.9-GHz-bandwidth 2 × 4-array stacked 5.3-GHz CMOS power amplifier,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, 2013, pp. 88–89.
[6] J.-H. Tsai, C.-F. Lin, P.-C. Shen, and H.-W. Ou-Yang, “A 5.2-GHz half-watt fully integrated CMOS power amplifier,” in Proc. IEEE 8th Global Conf. Consumer Electron. (GCCE), Osaka, Japan, 2019, pp. 407–408.
[7] M. Fathi, D. K. Su, and B. A. Wooley, “A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), San Jose, CA, USA, 2010, pp. 1–4.
[8] J.-H. Tsai, “Design of a 5.2-GHz CMOS power amplifier using TF-based 2-stage dual-radial power splitting/combining architecture,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 10, pp. 3690–3699, Oct. 2019.
[9] H.-C. Lin, H.-Z. Liao, D.-C. Chang, and H.-K. Chiou, “A highly linear stacked CMOS power amplifier with cold-FET linearizer for sub-6 GHz applications,” in Proc. IEEE Asia-Pacific Microw. Conf. (APMC), Bali, Indonesia, 2024, pp. 952–954.
[10] D. J. Niven, S. J. Mahon, and M. C. Heimlich, “X-band GaAs stacked-FET amplifier,” in Proc. IEEE Asia-Pacific Microw. Conf. (APMC), Brisbane, Australia, 2021, pp. 115–117.
[11] D. He, J. Wang, C. Tan, and Z. Yu, “A 1-W X-band high-efficiency power amplifier in 0.15-μm GaAs pHEMT technology,” in Proc. IEEE MTT-S Int. Wireless Symp. (IWS), Qingdao, China, 2023, pp. 1–3.
[12] X. Wang, M. Li, Q. Wang, L. Luo, Y. Liu, and J. Zhang, “A 7–13-GHz broadband high-efficiency MMIC power amplifier using second harmonic inductively tuning network,” IEEE Microw. Wirel. Technol. Lett., vol. 35, no. 4, pp. 484–487, Apr. 2025.
[13] Q. Cai, W. Che, K. Ma, and Q. Xue, “A compact Ku-band broadband GaAs power amplifier using an improved Darlington power stage,” IEEE Trans. Microw. Theory Techn., vol. 68, no. 7, pp. 3068–3078, Jul. 2020.
[14] K. P. Jung et al., “A Ku-band input harmonically tuned Class-F GaAs MMIC power amplifier achieving 28.4-dBm Psat and 56% peak PAE,” in Proc. IEEE/MTT-S Int. Microw. Symp. (IMS), San Francisco, CA, USA, 2025, pp. 452–455.
[15] X. Wang, Y. Liu, M. Li, Q. Wang, L. Luo, and J. Zhang, “A compact wideband high-efficiency power amplifier for Ku-band applications,” in Proc. Int. Conf. Microw. Millim. Wave Technol. (ICMMT), Beijing, China, 2024, pp. 1–3.
[16] I. Ju, H.-G. Ji, and I.-B. Yom, “Ku-band GaAs MMIC high-power amplifier with high efficiency and broadband,” in Proc. Conf. Microw. Techn. (COMITE), Pardubice, Czech Republic, 2015, pp. 1–4.
[17] Y. S. Noh and I. B. Yom, “Ku-band MMIC power amplifier with on-chip compensation gate bias circuit,” in Proc. Asia-Pacific Microw. Conf. (APMC), Hong Kong, China, 2008, pp. 1–4.
[18] H. Asada, K. Matsushita, K. Bunsen, K. Okada, and A. Matsuzawa, “A 60-GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16% PAE,” in Proc. IEEE Eur. Microw. Integr. Circuits Conf. (EuMIC), Manchester, U.K., Oct. 2011, pp. 554–557.
[19] W. L. Chan and J. R. Long, “A 58–65-GHz neutralized CMOS power amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2010.
[20] S. N. Ali et al., “A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable gate–drain neutralization for 28-GHz 5G radios,” IEEE Trans. Microw. Theory Techn., vol. 66, no. 5, pp. 2231–2245, May 2018.
[21] N. Deferm and P. Reynaert, “Differential and common-mode stability analysis of differential mm-wave CMOS amplifiers with capacitive neutralization,” Analog Integr. Circuits Signal Process., vol. 80, no. 1, pp. 1–12, Jul. 2014.
[22] H. Jia, C. C. Prawoto, B. Chi, Z. Wang, and C. P. Yue, “A full Ka-band power amplifier with 32.9% PAE and 15.3-dBm power in 65-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 9, pp. 2657–2668, Sep. 2018.
[23] R. Wang, C. Li, K. Qiu, Y. Liu, S. Yin, and Y. Wang, “A Ka-band broadband power amplifier with transformer-based lossy magnetically coupled resonator network: Analysis and design,” IEEE Trans. Microw. Theory Techn., vol. 72, no. 12, pp. 6857–6870, Dec. 2024.
[24] Z.-H. Fu, “Design and analysis of millimeter-wave wideband high-power GaAs power amplifier and distributed active transformer CMOS power amplifier with inductive compensation,” Ph.D. dissertation, Graduate Inst. Commun. Eng., National Taiwan Univ., Taipei, Taiwan, 2024.
[25] Cernexwave, Power Dividers/Combiners, product catalog, Jan. 2019. Accessed: Jul. 9, 2026. [Online]. Available: https://cernexwave.com/wp-content/uploads/2020/01/Cernexwave-power_dividers_combiners.pdf
[26] Transcom, Inc., TC5287P: 26.5–30.0-GHz 2-W 3-Stage PA MMIC, Package Form, datasheet. Accessed: Jul. 9, 2026. [Online]. Available: https://www.transcominc.com.tw/product_download_file.php?arg=B8Evxhcq3487THrlpbYlko6nU4q0nOa%2FrmdnKBfcJl6zrBowKC1%2BO%2Bh5cYCpRRAfeXRNFttzGtKJ%2Fh2mq6LL5Fmn1ocgD4yXJIvfjycY4LYe3EGmBVE
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104856-
dc.description.abstract此論文分為三個主要部分,分別探討應用於無線區域網路之 4.5–7.5 GHz 瓦特級 CMOS 功率放大器、應用於 FR3 相關微波通訊之 10–15 GHz GaAs pHEMT 寬頻高功率放大器,以及應用於 FR2 毫米波通訊之 28 GHz Ka-band GaAs 功率放大器模組。研究內容涵蓋功率放大器晶片設計、寬頻匹配網路、穩定度分析、被動結構損耗、功率合成及散熱設計。
第一部分介紹使用 90-nm CMOS 製程實現之 4.5–7.5 GHz 寬頻功率放大器。此電路採用兩級全差動架構,包含共源極驅動級與疊接式功率級,並於兩級放大器中加入交叉耦合中和電容,以降低電晶體閘極與汲極間寄生電容所造成之回授效應。輸入、級間及輸出匹配網路皆採用磁耦合共振器變壓器,以實現寬頻阻抗轉換及差動功率合成。量測結果顯示,此功率放大器之最大小訊號增益為 28.7 dB,飽和輸出功率為 29.3 dBm,輸出 1-dB 壓縮點為 24.5 dBm,峰值功率附加效率為 24.3%,整體晶片面積為 0.88 mm²。
第二部分介紹使用 0.15-μm GaAs pHEMT 製程實現之 10–15 GHz 寬頻高功率放大器。此電路採用兩級共源極架構,設計中使用寬頻輸入、級間與輸出匹配網路,並加入奇模穩定電阻及 RC 穩定網路,以提升多指電晶體與功率合成路徑之穩定度。量測結果顯示,在 10–15 GHz 頻段內,小訊號增益為 19.3–22.8 dB,飽和輸出功率為 31.85–33.09 dBm,輸出 1-dB 壓縮點為 30.28–32.55 dBm,功率附加效率為 35.75%–37.86%,整體晶片面積為 4.47 mm²。
第三部分介紹 28 GHz Ka-band GaAs 功率放大器模組之設計與量測。本研究完成 PCB 被動結構、單一 PA 模組及兩路功率合成模組之實作與特性分析,並分別使用 Wilkinson power divider/combiner、branch-line coupler 及 commercial divider/combiner module 實現三種 two-way power-combining PA module。量測結果顯示,三種模組之飽和輸出功率分別為 30.2、31.3 及 32.2 dBm,對應增益分別為 16.1、30.4 及 33.1 dB。此外,透過 Ansys Icepak 熱模擬與紅外線熱像量測,驗證銅製散熱結構可有效改善功率放大器模組之散熱能力。
zh_TW
dc.description.abstractThis thesis consists of three main parts: a 4.5–7.5 GHz watt-level CMOS power amplifier for wireless local area network applications, a 10–15 GHz broadband GaAs pHEMT high-power amplifier for FR3-related microwave communication applications, and a 28 GHz Ka-band GaAs power amplifier module for FR2 millimeter-wave communication applications. The research covers power amplifier IC design, broadband matching networks, stability analysis, passive-structure loss characterization, power combining, and thermal design.
The first part presents a 4.5–7.5 GHz broadband power amplifier implemented in a 90-nm CMOS technology. The proposed PA adopts a two-stage fully differential architecture consisting of a common-source driver stage and a cascode power stage. Cross-coupled neutralization capacitors are incorporated into both stages to reduce the feedback caused by the parasitic gate-to-drain capacitance of the transistors. Magnetically coupled resonator transformers are employed in the input, interstage, and output matching networks to achieve broadband impedance transformation and differential power combining. The measurement results show that the PA achieves a maximum small-signal gain of 28.7 dB, a saturated output power of 29.3 dBm, an output 1-dB compression point of 24.5 dBm, and a peak power-added efficiency of 24.3%. The total chip area is 0.88 mm².
The second part presents a 10–15 GHz broadband high-power amplifier implemented in a 0.15-μm GaAs pHEMT technology. The proposed PA adopts a two-stage common-source architecture with broadband input, interstage, and output matching networks. Odd-mode stabilization resistors and RC stabilization networks are also incorporated to improve the stability of the multi-finger transistors and power-combining paths. Across the 10–15 GHz operating band, the measured small-signal gain ranges from 19.3 to 22.8 dB, the saturated output power ranges from 31.85 to 33.09 dBm, the output 1-dB compression point ranges from 30.28 to 32.55 dBm, and the power-added efficiency ranges from 35.75% to 37.86%. The total chip area is 4.47 mm².
The third part presents the design and measurement of a 28 GHz Ka-band GaAs power amplifier module. PCB passive structures, unit PA modules, and two-way power-combining PA modules are implemented and characterized. Three two-way power-combining PA modules are realized using a Wilkinson power divider/combiner, a branch-line coupler, and commercial divider/combiner modules. The measured saturated output powers of the three modules are 30.2, 31.3, and 32.2 dBm, respectively, with corresponding gains of 16.1, 30.4, and 33.1 dB. In addition, thermal simulation using Ansys Icepak and infrared thermal imaging measurements verify that the proposed copper heat-spreading structure effectively improves the thermal performance of the PA module.
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dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-09-02T16:37:02Z
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dc.description.provenanceMade available in DSpace on 2026-09-02T16:37:02Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontents口試委員審定書 i
誌謝 ii
中文摘要 iv
ABSTRACT vi
CONTENTS viii
LIST OF FIGURES xi
LIST OF TABLES xix
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Literature Survey 3
1.3 Contributions 9
1.4 Thesis Organization 11
Chapter 2 4.5-7.5 GHz 90nm CMOS Power Amplifier 12
2.1 Introduction 12
2.2 Circuit Design 13
2.2.1 Overall Schematic of the Two-Stage Power Amplifier 13
2.2.2 Power-Stage and Matching Network 15
2.2.3 Driver-Stage and Matching Network 41
2.2.4 Circuit Layout and Simulation Results 56
2.3 Measurement Results and Debugging Analysis 63
2.3.1 Measurement Results 63
2.3.2 Debugging Analysis 70
2.4 Discussion and Summary 78
2.4.1 Gain-Budget Analysis of the Complete PA 78
2.4.2 Performance Comparison and Chapter Summary 83
Chapter 3 10-15 GHz High-power GaAs pHEMT Power Amplifier 87
3.1 Introduction 87
3.2 Circuit Design 88
3.2.1 Overall Schematic of the Two-Stage Power Amplifier 88
3.2.2 Power-stage and Matching Network 90
3.2.3 Driver-Stage and Matching Network 99
3.2.4 Circuit Layout and Simulation Results 106
3.3 Measurement Results and Debugging Analysis 115
3.3.1 Measurement Results 115
3.3.2 Debugging Analysis 124
3.4 Discussion and Summary 131
Chapter 4 Ka-band GaAs Power Amplifier Module 139
4.1 Introduction 139
4.2 Design Considerations for the Ka-band PA Module 140
4.3 Passive Characterization and Loss Evaluation 144
4.3.1 CPWG Transmission Line and End-Launch Connector Loss 144
4.3.2 Planar Power Divider/Combiner: Wilkinson Divider/Combiner and Branch-Line Coupler 147
4.3.3 Commercial Divider/Combiner Module 155
4.4 Unit PA Module Design and Measurement Results 159
4.5 Two-Way Power-Combining PA Module Design and Measurement Results 167
4.6 Thermal Simulation and Measurement 174
4.7 Discussion and Summary 180
Chapter 5 Conclusion 184
REFERENCE 187
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dc.language.isoen-
dc.subject功率放大器-
dc.subjectCMOS-
dc.subjectGaAs pHEMT-
dc.subject寬頻-
dc.subject功率合成-
dc.subject毫米波模組-
dc.subjectpower amplifier-
dc.subjectCMOS-
dc.subjectGaAs pHEMT-
dc.subjectbroadband-
dc.subjectpower combining-
dc.subjectmillimeter-wave module-
dc.title應用於無線區域網路之瓦特級 CMOS 功率放大器與行動通訊 FR3/FR2 砷化鎵功率放大器晶片/模組之研製zh_TW
dc.titleDevelopment of Watt-Level CMOS Power Amplifiers for WLAN and GaAs FR3/FR2 Power Amplifier IC/Module for Mobile Communicationsen
dc.typeThesis-
dc.date.schoolyear114-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee李俊興;蔡政翰;張鴻埜zh_TW
dc.contributor.oralexamcommitteeChun-Hsing Li;Jeng-Han Tsai;Hong-Yeh Changen
dc.subject.keyword功率放大器; CMOS; GaAs pHEMT; 寬頻; 功率合成; 毫米波模組zh_TW
dc.subject.keywordpower amplifier; CMOS; GaAs pHEMT; broadband; power combining; millimeter-wave moduleen
dc.relation.page190-
dc.identifier.doi10.6342/NTU202604184-
dc.rights.note同意授權(限校園內公開)-
dc.date.accepted2026-08-13-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電信工程學研究所-
dc.date.embargo-lift2029-07-31-
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