針對時序、功耗與面積協同最佳化之多位元正反器合併與擺置聯合解析框架

Abstract

擺置後 (post-placement) 的多位元正反器 (multi-bit flip-flop, MBFF) 合併能有效降低功耗 (power) 與面積 (area)。然而，僅於固定的輸入擺置 (placement) 上評估合併結果會限制解空間 (solution space)，可能排除掉當擺置與合併共同最佳化 (co-optimization) 時才會浮現的更佳組態。因此，本論文提出一個統一的解析式 (analytical) 多位元正反器合併與擺置框架，能在滿足產業界相容性 (compatibility) 限制的同時，協同最佳化時序 (timing)、功耗與面積。本框架結合了 (1) 高效率的時序與功耗模型 (timing and power model)、(2) 優先權多重密度圖 (prioritized multi-density map)，以及 (3) 合併親和性 (clustering-affinity) 機制；三者共同引導正反器 (flip-flop) 移動至適合合併的區域，並實現擺置與合併的整合最佳化。在 2025 年積體電路電腦輔助設計軟體製作競賽 (2025 CAD Contest at ICCAD) 之「使用多位元正反器之功耗與時序最佳化」題目中，本框架勝過所有參賽隊伍，且是唯一能在所有測試案例 (testcase) 上產生合法解 (valid solution) 的方法。我們進一步指出競賽元件庫 (cell library) 中的基準失衡 (benchmark imbalance) 問題，並提出一個能更真實反映合併效能的完善元件庫 (refined library)；在此完善之下，本方法仍維持一致的領先。最後，藉由放寬固定組合邏輯閘 (combinational gate) 的限制，我們將框架延伸為一套完整的產業界多位元正反器最佳化流程 (optimization flow)，其在多位元正反器合併、時序、功耗與面積上均勝過一套開源工具。

Post-placement multi-bit flip-flop (MBFF) clustering effectively reduces power and area. However, evaluating clustering solely on a fixed input placement constrains the solution space, potentially excluding better configurations that emerge when placement and clustering are co-optimized. Therefore, this thesis presents a unified analytical multi-bit flip-flop (MBFF) clustering and placement framework that addresses industrial compatibility constraints while jointly optimizing timing, power, and area. Our framework combines (1) efficient timing and power models, (2) prioritized multi-density maps, and (3) a clustering-affinity mechanism. Together, they guide flip-flops toward merging-friendly regions and enable integrated placement and clustering. Our framework outperforms all teams in the 2025 CAD Contest at ICCAD on Power and Timing Optimization Using Multi-Bit Flip-Flops, being the only approach to generate valid solutions across all testcases. We further identify a benchmark imbalance in the contest cell library and propose a refined library that better reflects clustering performance. Our method remains consistently superior under this refinement. Finally, by relaxing the constraint that fixes combinational gates, we extend the framework to a complete industrial MBFF optimization flow that improves the overall solution quality over an open-source tool.