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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | zh_TW |
| dc.contributor.advisor | Yao-Wen Chang | en |
| dc.contributor.author | 蘇絹淇 | zh_TW |
| dc.contributor.author | Chuan-Chi Su | en |
| dc.date.accessioned | 2026-09-02T16:34:26Z | - |
| dc.date.available | 2026-09-03 | - |
| dc.date.copyright | 2026-09-02 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-08-11 19:08:57 | - |
| dc.identifier.citation | [1] 2024 CAD Contest at ICCAD, Power and Timing Optimization Using Multibit Flip-Flop. [Online]. Available: https://www.iccad-contest.org/2024
[2] 2025 CAD Contest at ICCAD, Power and Timing Optimization Using Multibit Flip-Flop. [Online]. Available: https://www.iccad-contest.org/2025 [3] Y. Attaoui, M. Chentouf, Z. E. A. Alaoui Ismaili, and A. El Mourabit, "A new MBFF merging strategy for post-placement power optimization of IoT devices," in Proc. of IEEE/ACS AICCSA, Tunis, Tunisia, December 2021. [4] J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009. [5] Y.-C. Chang, T.-W. Lin, I.-R. Jiang, and G.-J. Nam, "Graceful register clustering by effective mean shift algorithm for power and timing balancing," in Proc. of ISPD, pp. 11–18, New York, NY, USA, April 2019. [6] Y.-T. Chang, C.-C. Hsu, M. P.-H. Lin, Y.-W. Tsai, and S.-F. Chen, "Post-placement power optimization with multi-bit flip-flops," in Proc. of ICCAD, pp. 218–223, San Jose, CA, USA, 2010. [7] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," IEEE Tran. on CAD, vol. 27, no. 7, pp. 1228–1240, 2008. [8] Y.-Y. Chen, H.-Y. Wu, I.-R. Jiang, C.-H. Tsai, and C.-C. Wu, "Slack redistributed register clustering with mixed-driving strength multi-bit flip-flops," in Proc. of ISPD, pp. 21–29, New York, NY, USA, March 2024. [9] C. Feng, D. Yue, Z. Zhao, and Z. Liao, "A parameterized timing-aware flip-flop merging algorithm for clock power reduction," in Proc. of DATE, pp. 881–884, Dresden, Germany, March 2018. [10] S. Izquierdo, J. Guerrero-Viu, S. Hauns, G. Miotto, S. Schrodi, A. Biedenkapp, T. Elsken, D. Deng, M. Lindauer, and F. Hutter, "Bag of baselines for multi-objective joint neural architecture search and hyperparameter optimization," in Proc. of AutoML Conf., pp. 1–16, Virtual, July 2021. [11] I. H.-R. Jiang, C.-L. Chang, and Y.-M. Yang, "Integra: Fast multibit flip-flop clustering for clock power saving," IEEE Tran. on CAD, vol. 31, no. 2, pp. 192–204, 2012. [12] A. Kahng, S. Kundu, and S. Thumathy, "Scalable flip-flop clustering using divide and conquer for capacitated k-means," in Proc. of GLCLSI, pp. 177–184, Clearwater, FL, USA, 2024. [13] A. B. Kahng, J. Li, and L. Wang, "Improved flop tray-based design implementation for power reduction," in Proc. of ICCAD, pp. 1–8, Austin, TX, USA, November 2016. [14] A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," IEEE Tran. on CAD, vol. 24, no. 5, pp. 734–747, 2005. [15] C.-Y. Li, C.-C. Su, Z.-W. Chen, S.-H. Chen, and Y.-W. Chang, "Late breaking results: Multi-objective multi-bit flip-flop placement considering pre-placed cells," in Proc. of DAC, pp. 1–2, San Francisco, CA, USA, June 2025. [16] ——, "Multi-objective multi-bit flip-flop placement considering pre-placed cells," IEEE Tran. on CAD, pp. 1–10, 2026. [17] M.-Y. Liu, Y.-C. Lai, W.-K. Mak, and T.-C. Wang, "Generation of mixed-driving multi-bit flip-flops for power optimization," in Proc. of ICCAD, pp. 1–9, San Diego, CA, USA, 2022. [18] Y.-C. Lu, Z. Guo, K. Kunal, R. Liang, and H. Ren, "INSTA: An ultra-fast, differentiable, statistical static timing analysis engine for industrial physical design applications," in Proc. of DAC, pp. 1–7, 2025. [19] H. Moon and T. Kim, "Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization," in Proc. of ASPDAC, pp. 268–273, Macao, China, January 2016. [20] W. C. Naylor, R. Donelly, and L. Sha, "Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer," US Patent 6,301,693, October 2001. [21] I. Seitanidis, G. Dimitrakopoulos, P. M. Mattheakis, L. Masse-Navette, and D. Chinnery, "Timing-driven and placement-aware multibit register composition," IEEE Tran. on CAD, vol. 38, no. 8, pp. 1501–1514, 2019. [22] P. Spindler, U. Schlichtmann, and F. M. Johannes, "Abacus: Fast legalization of standard cell circuits with minimal movement," in Proc. of ISPD, pp. 47–53, Portland, OR, USA, April 2008. [23] The OpenROAD Project, "OpenROAD: An open-source, foundational application for semiconductor digital design," https://github.com/The-OpenROAD-Project/OpenROAD, accessed: 2026-06-04. [24] C.-C. Tsai, Y. Shi, G. Luo, and I. H.-R. Jiang, "FF-Bond: Multi-bit flip-flop bonding at placement," in Proc. of ISPD, pp. 147–153, Stateline, NV, USA, March 2013. [25] Z. Wang, S. Liu, Y. Pu, S. Chen, T.-Y. Ho, and B. Yu, "PRO-TIME: Prerouting optimization-aware timing prediction via multimodal learning," IEEE Tran. on CAD, vol. 44, no. 12, pp. 4779–4792, 2025. [26] C. Xu, P. Li, G. Luo, Y. Shi, and I. H.-R. Jiang, "Analytical clustering score with application to post-placement multi-bit flip-flop merging," in Proc. of ISPD, pp. 93–100, Monterey, CA, USA, March 2015. [27] S.-W. Yang, J.-W. Hsu, Y.-H. Cheng, and C.-F. Shen, "Invited paper 2025 ICCAD CAD Contest problem B: Power and timing optimization using multibit flip-flop," in Proc. of ICCAD, pp. 1–6, Munich, Germany, October 2025. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104849 | - |
| dc.description.abstract | 擺置後 (post-placement) 的多位元正反器 (multi-bit flip-flop, MBFF) 合併能有效降低功耗 (power) 與面積 (area)。然而，僅於固定的輸入擺置 (placement) 上評估合併結果會限制解空間 (solution space)，可能排除掉當擺置與合併共同最佳化 (co-optimization) 時才會浮現的更佳組態。因此，本論文提出一個統一的解析式 (analytical) 多位元正反器合併與擺置框架，能在滿足產業界相容性 (compatibility) 限制的同時，協同最佳化時序 (timing)、功耗與面積。本框架結合了 (1) 高效率的時序與功耗模型 (timing and power model)、(2) 優先權多重密度圖 (prioritized multi-density map)，以及 (3) 合併親和性 (clustering-affinity) 機制；三者共同引導正反器 (flip-flop) 移動至適合合併的區域，並實現擺置與合併的整合最佳化。在 2025 年積體電路電腦輔助設計軟體製作競賽 (2025 CAD Contest at ICCAD) 之「使用多位元正反器之功耗與時序最佳化」題目中，本框架勝過所有參賽隊伍，且是唯一能在所有測試案例 (testcase) 上產生合法解 (valid solution) 的方法。我們進一步指出競賽元件庫 (cell library) 中的基準失衡 (benchmark imbalance) 問題，並提出一個能更真實反映合併效能的完善元件庫 (refined library)；在此完善之下，本方法仍維持一致的領先。最後，藉由放寬固定組合邏輯閘 (combinational gate) 的限制，我們將框架延伸為一套完整的產業界多位元正反器最佳化流程 (optimization flow)，其在多位元正反器合併、時序、功耗與面積上均勝過一套開源工具。 | zh_TW |
| dc.description.abstract | Post-placement multi-bit flip-flop (MBFF) clustering effectively reduces power and area. However, evaluating clustering solely on a fixed input placement constrains the solution space, potentially excluding better configurations that emerge when placement and clustering are co-optimized. Therefore, this thesis presents a unified analytical multi-bit flip-flop (MBFF) clustering and placement framework that addresses industrial compatibility constraints while jointly optimizing timing, power, and area. Our framework combines (1) efficient timing and power models, (2) prioritized multi-density maps, and (3) a clustering-affinity mechanism. Together, they guide flip-flops toward merging-friendly regions and enable integrated placement and clustering. Our framework outperforms all teams in the 2025 CAD Contest at ICCAD on Power and Timing Optimization Using Multi-Bit Flip-Flops, being the only approach to generate valid solutions across all testcases. We further identify a benchmark imbalance in the contest cell library and propose a refined library that better reflects clustering performance. Our method remains consistently superior under this refinement. Finally, by relaxing the constraint that fixes combinational gates, we extend the framework to a complete industrial MBFF optimization flow that improves the overall solution quality over an open-source tool. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-09-02T16:34:26Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-09-02T16:34:26Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員審定書 ii
Declaration iii Acknowledgements iv 摘要 v Abstract vii Table of Contents ix List of Tables xii List of Figures xiii Chapter 1. Introduction 1 1.1 Previous Work 2 1.1.1 Integration of Clustering and Placement 2 1.1.2 Compatibility Constraint 3 1.1.3 Co-optimization of Timing, Power, and Area 4 1.2 Motivation 5 1.3 Our Contributions 6 1.4 Thesis Organization 8 Chapter 2. Preliminaries 9 2.1 Problem Formulation 9 2.2 Timing and Power Estimation in Commercial Tools 12 2.3 Analytical Placement 13 Chapter 3. Methodology 15 3.1 Timing and Power Model Construction 16 3.1.1 Timing Model 17 3.1.2 Power Model 18 3.2 Declustering and Flip-Flop Sizing 18 3.2.1 Multi-Bit Flip-Flop Declustering 18 3.2.2 Flip-Flop Sizing 19 3.3 MBFF Clustering and Placement 19 3.3.1 Compatible Group Construction and Prioritization 19 3.3.2 Analytical Flip-Flop Relocation 20 3.3.2.1 Timing Model 21 3.3.2.2 Density Penalty 22 3.3.2.3 Clustering Affinity 25 3.3.2.4 Freeze Mechanism 26 Condition 1 (Score check). 27 Condition 2 (Gradient alignment). 28 3.3.2.5 Optimization 29 Phase 1: Timing-Only Optimization. 30 Phase 2: Timing and Density Co-Optimization. 31 Phase 3: Full Co-Optimization with Clustering Affinity. 32 3.3.3 k-Bit Flip-Flop Clustering and Legalization 33 3.3.4 k-Bit Flip-Flop Declustering and Legalization 35 Chapter 4. Experimental Results 37 4.1 Experimental Setup 37 4.2 Benchmark Statistics 38 4.3 Comparison under the Original Library 39 4.4 Comparison under the Refined Library 39 4.5 Timing and Power Model Accuracy 41 4.6 Comparison with OpenROAD under the Movable-Gate Flow 44 4.6.1 Layout Visualizations 46 Chapter 5. Conclusions and Future Works 52 5.1 Conclusions 52 5.2 Future Works 53 5.2.1 Full Movable-Gate Analytical Placement 53 5.2.2 Scan-Chain Compatibility Constraint 53 Bibliography 55 Publication List 59 | - |
| dc.language.iso | en | - |
| dc.subject | 實體設計 | - |
| dc.subject | 多位元正反器合併 | - |
| dc.subject | 解析式擺置 | - |
| dc.subject | 時序最佳化 | - |
| dc.subject | 功耗最佳化 | - |
| dc.subject | 擺置合法化 | - |
| dc.subject | Physical Design | - |
| dc.subject | Multi-Bit Flip-Flop Clustering | - |
| dc.subject | Analytical Placement | - |
| dc.subject | Timing Optimization | - |
| dc.subject | Power Optimization | - |
| dc.subject | Placement Legalization | - |
| dc.title | 針對時序、功耗與面積協同最佳化之多位元正反器合併與擺置聯合解析框架 | zh_TW |
| dc.title | A Unified Analytical Framework for MBFF Clustering and Placement for Timing, Power, and Area Co-Optimization | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃婷婷;江蕙如 | zh_TW |
| dc.contributor.oralexamcommittee | Ting-Ting Hwang;Iris Hui-Ru Jiang | en |
| dc.subject.keyword | 實體設計; 多位元正反器合併; 解析式擺置; 時序最佳化; 功耗最佳化; 擺置合法化 | zh_TW |
| dc.subject.keyword | Physical Design; Multi-Bit Flip-Flop Clustering; Analytical Placement; Timing Optimization; Power Optimization; Placement Legalization | en |
| dc.relation.page | 59 | - |
| dc.identifier.doi | 10.6342/NTU202602995 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2026-08-14 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 積體電路設計與自動化學位學程 | |
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