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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 資訊工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10479
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor楊佳玲
dc.contributor.authorI-Hsien Linen
dc.contributor.author林怡賢zh_TW
dc.date.accessioned2021-05-20T21:32:49Z-
dc.date.available2013-08-19
dc.date.available2021-05-20T21:32:49Z-
dc.date.copyright2010-08-19
dc.date.issued2010
dc.date.submitted2010-08-17
dc.identifier.citation[1] C. Bienia, S. Kumar, and K. Li. Parsec vs. splash-2: A quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors. In Proceedings of the 2008 International Symposium on Workload Characterization, September 2008.
[2] C. Bienia, S. Kumar, J. P. Singh, and K. Li. The parsec benchmark suite: characterization and architectural implications. In PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques, pages 72–81, New York, NY, USA, 2008. ACM.
[3] C. Bienia and K. Li. Parsec 2.0: A new benchmark suite for chip-multiprocessors. In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, June 2009.
[4] F. Black and M. S. Scholes. The pricing of options and corporate liabilities. Journal of Political Economy, 81(3):637–54, May-June 1973.
[5] L. Cheng, J. B. Carter, and D. Dai. An adaptive cache coherence protocol optimized for producer-consumer sharing. In HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pages 328–339, Washington, DC, USA, 2007. IEEE Computer Society.
[6] M. Dubois, J. Skeppstedt, L. Ricciulli, K. Ramamurthy, and P. Stenstr¨om. The detection and elimination of useless misses in multiprocessors. SIGARCH Comput. Archit. News, 21(2):88–97, 1993.
[7] J. Huh, J. Chang, D. Burger, and G. S. Sohi. Coherence decoupling: making use of incoherence. SIGARCH Comput. Archit. News, 32(5):97–106, 2004.
[8] S. Kaxiras and J. R. Goodman. Improving cc-numa performance using instruction-based prediction. In HPCA '99: Proceedings of the 5th International Symposium on High Performance Computer Architecture, page 161, Washington, DC, USA, 1999. IEEE Computer Society.
[9] A.-C. Lai and B. Falsafi. Memory sharing predictor: the key to a speculative coherent dsm. SIGARCH Comput. Archit. News, 27(2):172–183, 1999.
[10] K. M. Lepak and M. H. Lipasti. Silent stores for free. In MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, pages 22–31, New York, NY, USA, 2000. ACM.
[11] K. M. Lepak and M. H. Lipasti. Temporally silent stores. SIGARCH Comput. Archit. News, 30(5):30–41, 2002.
[12] P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. H˚allberg, J. H¨ogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. Computer, 35(2):50–58, 2002.
[13] M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News, 33(4):92–99, 2005.
[14] S. S. Mukherjee and M. D. Hill. Using prediction to accelerate coherence protocols. SIGARCH Comput. Archit. News, 26(3):179–190, 1998.
[15] J. P. Singh, W. Weber, and A. Gupta. Splash: Stanford parallel applications for shared-memory. Technical report, Stanford, CA, USA, 1991.
[16] S. Somogyi, T. F.Wenisch, A. Ailamaki, and B. Falsafi. Spatio-temporal memory streaming. SIGARCH Comput. Archit. News, 37(3):69–80, 2009.
[17] T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi. Temporal streaming of shared memory. In ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture, pages 222–233, Washington, DC, USA, 2005. IEEE Computer Society.
[18] S. C.Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The splash-2 programs: characterization and methodological considerations. In ISCA '95: Proceedings of the 22nd annual international symposium on Computer architecture, pages 24–36, New York, NY, USA, 1995. ACM.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10479-
dc.description.abstract在這篇論文中,我們首先試著去分析PARSEC與SPLASH-2這兩個常用的評測基準程式(benchmark suite)之工作特性。每個工作量(workload)都會在各種不同的模擬機器配置下進行實驗來研究他們多樣化的特性。此外,我們也試著啟動一個軟體預取機制(software prefetching scheme)來評估對這些不同工作量所造成的影響。根據這些實驗,我們發現到當執行這些工作量時,在互連網路上常常會有大量對共享資料做讀取動作的傳輸。
針對平行程式中大量的共享資料讀取失誤,我們提出一個稱為Snooping Fetch (SF)的方法。這個方法藉由系統中固有的快取一致性協定(cache coherence protocol)以及監聽協定(snooping protocol)所廣播的資訊來試著減少這些共享資料的讀取失誤。我們可以利用這個廣播的特性,在一筆資料真正要被使用之前先把資料讀進快取記憶體中以隱藏讀取時的延遲。在我們的實驗中,這個方法針對減少L1快取記憶體失誤量的部分可以得到平均8%的可能性,而在L1快取失誤率的減少量約有平均0.5%的可能性,以及平均0.4%的效能加速可能性。
zh_TW
dc.description.abstractIn this thesis, we first characterize two popular benchmark suites, PARSEC and SPLASH-2. Different configurations of the simulated machine are set for each workload in the suites to study their diverse properties. Besides, we also try to evaluate the influence of different workloads when enabling a software prefetching scheme. Based on the experiments, we find that there is plenty of shared read traffic on the interconnection in these workloads.
To reduce these shared read misses, a policy, called Snooping Fetch (SF), is proposed for the shared data in parallelized applications, which takes advantage of the inherent cache coherence protocol and the broadcasting information from the snooping protocol. The SF policy utilizes the broadcasting property to fetch shared data before the data is actually needed. In our experiments, the SF policy provides a reduction potential of 8% in average in the amounts of L1 cache misses, a reduction potential of 0.5% in average in the L1 cache miss rate, and a potential of 0.4% speedup in average.
en
dc.description.provenanceMade available in DSpace on 2021-05-20T21:32:49Z (GMT). No. of bitstreams: 1
ntu-99-R96922148-1.pdf: 592885 bytes, checksum: 04cf54656912d7245302f82b3fad08ae (MD5)
Previous issue date: 2010
en
dc.description.tableofcontentsAbstract i
1 Introduction 1
2 Workloads 4
2.1 PARSEC Suite . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 SPLASH-2 Suite . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Simulation Setup 9
4 Workload Characterization 12
4.1 L1 Cache Size . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Cache Line Size . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Sharing Degree . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 Traffic Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Snooping Fetch 24
6 Evaluation of SF Policy 28
6.1 Traffic Breakdown Comparison . . . . . . . . . . . . . . . . . 29
6.2 Number of Cores . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 L1 Cache Miss Rate . . . . . . . . . . . . . . . . . . . 32
6.2.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 L1 Cache Size . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3.1 L1 Cache Miss Rate . . . . . . . . . . . . . . . . . . . 35
6.3.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . 37
7 Related Work 39
7.1 Workload Characterization . . . . . . . . . . . . . . . . . . . . 39
7.2 Hiding Data Access Latency . . . . . . . . . . . . . . . . . . . 40
8 Conclusions 43
Bibliography 45
dc.language.isoen
dc.titlePARSEC與SPLASH-2之工作特性分析zh_TW
dc.titleWorkload Characterization of PARSEC and SPLASH-2en
dc.typeThesis
dc.date.schoolyear98-2
dc.description.degree碩士
dc.contributor.oralexamcommittee洪士灝,施吉昇,謝仁偉
dc.subject.keywordPARSEC,SPLASH-2,評測基準程式,工作特性分析,預取,隱藏資料存取延遲,zh_TW
dc.subject.keywordPARSEC,SPLASH-2,benchmark suite,workload characterization,prefetch,data access latency hiding,en
dc.relation.page47
dc.rights.note同意授權(全球公開)
dc.date.accepted2010-08-18
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept資訊工程學研究所zh_TW
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