應用於多核心處理器具動態電壓頻率調控之基於全數位低壓差線性穩壓器分散式電源管理架構

Abstract

本作提出了一種用於系統單晶片 (SoC) 多核心處理器的全數位分散式電源管理架構，實現了精細且最佳化的動態電壓頻率調控技術 (DVFS)。傳統的 DVFS 和供電拓樸架構可擴展性和整合性不足，例如依賴晶片外部元件、類比控制迴路、需要參考電壓源、單輸出架構，對現代多核心系統的適用性較差。為了克服這些限制，本文提出了一個主從式全數位架構，為多核心電源管理提供了一個緊湊、可擴展且無需類比參考源的解決方案。 本作所提出的架構採用數位低壓差線性穩壓器 (DLDO) 進行電源分配，從而實現了高功率密度且完全整合至晶片中。透過整合頻率控制迴路和電壓調控迴路，該系統無需類比參考源即可自然收斂到最佳能量運用率的工作點。主單元透過鎖相操作確保全系統時脈穩定性，而從單元則作為鎖頻迴路 (FLL) 運行，從而能夠快速適應動態工作負載變化，實現電壓和頻率的快速自適應。由於其全數位化特性，所提出的控制方案與現代數位處理器環境高度相容，並且無需任何參考電壓源。每個負載運算核心均獲得獨立且客製化的供電電壓，使得該架構能在低於 1V 的低電壓下有效運作，並最大限度地降低了每次操作的能耗。 本次所提出的設計採用 28nm CMOS 製程實現，測量結果顯示其具有有效的動態電壓頻率調控 (DVFS) 功能、在負載變化下快速的瞬態響應，並且所提出的分散式電源管理方案適用於多核心處理器的應用。

This dissertation introduces an all-digital, fully integrated distributed power management architecture specifically designed for multi-core processors in system-on-chip (SoC) platforms, enabling fine-grained and tailored dynamic voltage and frequency scaling (DVFS). Conventional DVFS and power delivery architectures often suffer from limited scalability and integration challenges, including reliance on off-chip components, analog control loops, reference voltages, single-output regulation, and low suitability for modern multi-core systems. To address these limitations, this work proposes a master–slave all-digital architecture that provides a compact and scalable solution without requiring any DC reference voltages for multi-core power management. By leveraging an external reference frequency (FREF) as the sole baseline, the system successfully eliminates the need for traditional DC reference voltages and their associated analog circuits. The proposed architecture utilizes a digital low-dropout regulator (DLDO) for power delivery, providing high power density and enabling full on-chip integration. Furthermore, the unification of the frequency and voltage tracking loops allows the microprocessor to autonomously settle at a highly energy-efficient operating point without requiring analog references. The master cell ensures global clock stability through phase-locked operation, while slave cells operate as high-bandwidth frequency-locked loops (FLLs), enabling rapid voltage and frequency adaptation to dynamic workload variations. Because it is implemented entirely with standard cells, this architecture seamlessly merges with modern digital synthesis flows. Consequently, each sub-core receives an individually customized power supply, yielding exceptional efficiency, especially in sub-1V low-voltage operation level. The proposed design is implemented in a 28-nm CMOS process, with measurement results demonstrating effective DVFS operation, fast transient response under load variations, and the overall viability of this distributed scheme for next-generation multi-core SoCs.