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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103235完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳景然 | zh_TW |
| dc.contributor.advisor | Ching-Jan Chen | en |
| dc.contributor.author | 陳彥銘 | zh_TW |
| dc.contributor.author | Yen-Ming Chen | en |
| dc.date.accessioned | 2026-08-05T17:12:00Z | - |
| dc.date.available | 2026-08-06 | - |
| dc.date.copyright | 2026-08-05 | - |
| dc.date.issued | 2026 | - |
| dc.date.submitted | 2026-07-21 | - |
| dc.identifier.citation | [1] Y.-M. Chen, C.-J. Chen, and Y.-L. Chao, "An all-digital distributed power management architecture for dynamic voltage and frequency scaling (DVFS) for multi-core processor," IEEE Transactions on Industry Applications, vol. 62, no. 3, pp. 4259-4270, May-June 2026, doi: 10.1109/TIA.2025.3623071.
[2] C. Isci, A. Buyuktosunoglu, C. -y. Cher, P. Bose and M. Martonosi., ”An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget,” in Proc. IEEE/ACM International Symposium on Microarchitecture (MICRO'06), Orlando, FL, USA, 2006, pp. 347-358. [3] N. Hou, F. He, Y. Zhou, Y. Chen and X. Yan., ”A parallel genetic algorithm with dispersion correction for HW/SW partitioning on multi-core CPU and many-core GPU,” IEEE Access, vol. 6, pp. 883-898, 2018. [4] J. D. Owens, M. Houston, D. Luebke, S. Green, J. E. Stone and J. C. Phillips, "GPU Computing," in Proc. of the IEEE, vol. 96, no. 5, pp. 879-899, May 2008. [5] Blaise Barney, “Introduction to Parallel Computing Tutorial,” Livermore Computing, Donald Frederick, LLNL. [Online]. Available: https://hpc.llnl.gov/documentation/tutorials/introduction-parallel-computing-tutorial. [6] M. Ho, K. N. Leung, and K. L. Mak, “A low-power fast-transient 90-nm low-dropout regulator with multiple small-gain stages,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2466-2475, Nov. 2010. [7] J. Guo and K. N. Leung, “A 6-μW chip-area-efficient output capacitorless LDO in 90-nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1896-1905, Sept. 2010. [8] C. -Y. Tseng, L. -W. Wang and P. -C. Huang, "An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems," IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2239-2249, Nov. 2010. [9] S. B. Nasir, S. Gangopadhyay and A. Raychowdhury, "All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits," IEEE Transactions on Power Electronics, vol. 31, no. 12, pp. 8293-8302, Dec. 2016. [10] M. A. Akram, W. Hong and I. -C. Hwang, "Capacitorless Self-Clocked All-Digital Low-Dropout Regulator," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 266-276, Jan. 2019. [11] J. Oh, J. -E. Park, Y. H. Hwaung, and D. -K. Jeong, “A 480mA output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector with 99.99% current efficiency, 1.3ns response time, and 9.8A/mm2 current density,” in Proc. IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 382-384. [12] M. E. Perez, M. A. Sperling, J. F. Bulzacchelli, Z. Toprak-Deniz and T. E. Diemoz, "Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS," IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 731-743, March 2020. [13] S. Kaedi, M. B. Ghaznavi-Ghoushchi, and M. Rahimi, “A power efficient multi-level output all digital LDO with fast settling time and built in self calibration for DVFS and multi-VDD applications,” in Proc. IEEE Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, 2015, pp. 1276-1281. [14] S. Kundu, M. Liu, R. Wong, S. J. Wen, and C. H. Kim, “A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning,” in Proc. IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2018, pp. 308-310. [15] M. A. Akram, I. -C. Hwang and S. Ha, "Architectural Advancement of Digital Low-Dropout Regulators," IEEE Access, vol. 8, pp. 137838-137855, 2020. [16] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A dynamic voltage scaled microprocessor system,” IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000. [17] X. Liu, S. Li, and B. H. Calhoun,” An 802pW 93% peak efficiency buck converter with 5.5×106 dynamic range featuring fast dvfs and asynchronous load-transient control” in Proc. IEEE European Solid State Circuits Conference (ESSCIRC), Grenoble, France, 2021, pp. 347-350. [18] B. Labbé, P. Fan, T. Achuthan, P. Prabhat, G. P. Knight , and J. Myers, “A supply voltage control method for performance guaranteed ultra-low-power microcontroller,” IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 601–611, Feb. 2021. [19] Y. H. Lee et al., “A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 1018–1030, APR. 2013. [20] C. Schaef et al., “A fully integrated voltage regulator in 14 nm CMOS with package-embedded air-core inductor featuring self-trimmed, digitally controlled variable on-time discontinuous conduction mode operation,” in Proc. IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 154-156. [21] Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui and P. K. T. Mok, "Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode," IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 89-100, Jan. 2003. [22] C. -H. Huang, X. Sun, Y. Chen, R. Pamula, A. Mandal and V. Sathe, "29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS," in Proc. IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2021, pp. 416-418. [23] J. Jiang, Y. Lu, C. Huang, W.-H. Ki, and P. K. T. Mok, “A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement,” in Proc. IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2015, pp. 366–367. [24] A. Paul, D. Jiao, S. Sapatnekar and C. H. Kim,” Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, 2013, pp. 49-52. [25] S. Sidiropoulos, Dean Liu, Jaeha Kim, Guyeon Wei and M. Horowitz, "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," in Proc. IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2000, pp. 124-127. [26] R. B. Staszewski, D. Leipold and P. T. Balsara, "Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 887-892, Nov. 2003. [27] Bo Zhai, D. Blaauw, D. Sylvester and K. Flautner, "The limit of dynamic voltage scaling and insomniac dynamic voltage scaling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 11, pp. 1239-1252, Nov. 2005. [28] T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584-594, April 1990. [29] J. M. Rabaey, “Digital Integrated Circuits: A Design Perspective,” Chapter 3.3. [30] S. M. Sze and K. K. Ng, "Physics of Semiconductor Devices," 3rd ed., Wiley, 2006, Ch. 7. [31] M. Keating et al, “Low Power Methodology Manual For System-on-Chip Design,” Springer, 2007. [32] S. Narendra and A. Chandrakasan, “Leakage in Nanometer CMOS Technologies,” Springer, 2006. [33] Radhapuram and S. C. Teja, “Study on Behavior-Level Modeling and Top-Down Approach Design of All-Digital Phase-Locked Loop” The University of Osaka, 2020. [34] S. Kundu, M. Liu, S. -J. Wen, R. Wong and C. H. Kim, "A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 109-120, Jan. 2019. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/103235 | - |
| dc.description.abstract | 本作提出了一種用於系統單晶片 (SoC) 多核心處理器的全數位分散式電源管理架構，實現了精細且最佳化的動態電壓頻率調控技術 (DVFS)。傳統的 DVFS 和供電拓樸架構可擴展性和整合性不足，例如依賴晶片外部元件、類比控制迴路、需要參考電壓源、單輸出架構，對現代多核心系統的適用性較差。為了克服這些限制，本文提出了一個主從式全數位架構，為多核心電源管理提供了一個緊湊、可擴展且無需類比參考源的解決方案。
本作所提出的架構採用數位低壓差線性穩壓器 (DLDO) 進行電源分配，從而實現了高功率密度且完全整合至晶片中。透過整合頻率控制迴路和電壓調控迴路，該系統無需類比參考源即可自然收斂到最佳能量運用率的工作點。主單元透過鎖相操作確保全系統時脈穩定性，而從單元則作為鎖頻迴路 (FLL) 運行，從而能夠快速適應動態工作負載變化，實現電壓和頻率的快速自適應。由於其全數位化特性，所提出的控制方案與現代數位處理器環境高度相容，並且無需任何參考電壓源。每個負載運算核心均獲得獨立且客製化的供電電壓，使得該架構能在低於 1V 的低電壓下有效運作，並最大限度地降低了每次操作的能耗。 本次所提出的設計採用 28nm CMOS 製程實現，測量結果顯示其具有有效的動態電壓頻率調控 (DVFS) 功能、在負載變化下快速的瞬態響應，並且所提出的分散式電源管理方案適用於多核心處理器的應用。 | zh_TW |
| dc.description.abstract | This dissertation introduces an all-digital, fully integrated distributed power management architecture specifically designed for multi-core processors in system-on-chip (SoC) platforms, enabling fine-grained and tailored dynamic voltage and frequency scaling (DVFS). Conventional DVFS and power delivery architectures often suffer from limited scalability and integration challenges, including reliance on off-chip components, analog control loops, reference voltages, single-output regulation, and low suitability for modern multi-core systems. To address these limitations, this work proposes a master–slave all-digital architecture that provides a compact and scalable solution without requiring any DC reference voltages for multi-core power management. By leveraging an external reference frequency (FREF) as the sole baseline, the system successfully eliminates the need for traditional DC reference voltages and their associated analog circuits.
The proposed architecture utilizes a digital low-dropout regulator (DLDO) for power delivery, providing high power density and enabling full on-chip integration. Furthermore, the unification of the frequency and voltage tracking loops allows the microprocessor to autonomously settle at a highly energy-efficient operating point without requiring analog references. The master cell ensures global clock stability through phase-locked operation, while slave cells operate as high-bandwidth frequency-locked loops (FLLs), enabling rapid voltage and frequency adaptation to dynamic workload variations. Because it is implemented entirely with standard cells, this architecture seamlessly merges with modern digital synthesis flows. Consequently, each sub-core receives an individually customized power supply, yielding exceptional efficiency, especially in sub-1V low-voltage operation level. The proposed design is implemented in a 28-nm CMOS process, with measurement results demonstrating effective DVFS operation, fast transient response under load variations, and the overall viability of this distributed scheme for next-generation multi-core SoCs. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2026-08-05T17:12:00Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2026-08-05T17:12:00Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 II 中文摘要 V Abstract VI Table of Content VIII List of Tables X List of Figures XI Chapter 1. Introduction 1 1.1 Power Delivery in Multi-Core Processor 1 1.2 Brief Introduction of Digital Low-Dropout Regulator (DLDO) 5 1.3 Dynamic Voltage and Frequency Scaling (DVFS) 12 1.4 Thesis Organization 23 Chapter 2. Proposed Master-Slave ADPLL-based DLDO for DVFS 25 2.1 The Master-Slave Architecture 25 2.2 DVFS Operation 31 2.3 Power Consumption Reduction 35 Chapter 3. Small-Signal Transfer Function Modeling 43 3.1 From Conventional PLL (s-domain) to ADPLL (z-domain) 46 3.2 Digital Loop Filter in the z-domain 48 3.3 Modeling of DLDO Output Stage and Ring Oscillator (RO) 49 3.4 Master Cell — Like a PLL, Sampling at FREF 52 3.5 Slave Cell — Like an FLL, Sampling at FCLK 56 3.6 Stability Analysis 58 3.7 Short Summary 61 Chapter 4. Circuit Implementation 62 4.1 Ring Oscillator (RO) 64 4.2 Bang-Bang Phase-Frequency Detector (BBPFD) 69 4.3 Time-to-Digital Converter (TDC) 72 4.4 Digital Filter 75 4.5 Power-Saving Mode 77 Chapter 5. Measurement Results 79 5.1 The Test Chip 79 5.2 DVFS Operation 81 5.3 Load Transient Measurement 85 5.4 Comparison 89 5.1 Conclusion 91 5.2 Future Works 92 Reference 93 Vita 97 | - |
| dc.language.iso | en | - |
| dc.subject | 動態電壓頻率調控 (DVFS) | - |
| dc.subject | 數位低壓差線性穩壓器 (DLDO) | - |
| dc.subject | 全數位鎖相迴路 (AD-PLL) | - |
| dc.subject | 能源效率 | - |
| dc.subject | 低功耗 | - |
| dc.subject | 可拓展化 | - |
| dc.subject | 每秒百萬指令 (MIPS) | - |
| dc.subject | 系統單晶片 (SoC) | - |
| dc.subject | Dynamic voltage and frequency scaling (DVFS) | - |
| dc.subject | Digital low-dropout regulator (DLDO) | - |
| dc.subject | all-digital phase-locked loop (AD-PLL) | - |
| dc.subject | energy efficient | - |
| dc.subject | low power | - |
| dc.subject | scalability | - |
| dc.subject | million instructions per second (MIPS) | - |
| dc.subject | system-on-chip (SoC) | - |
| dc.title | 應用於多核心處理器具動態電壓頻率調控之基於全數位低壓差線性穩壓器分散式電源管理架構 | zh_TW |
| dc.title | An All-Digital Low-Dropout Based Distributed Power Management Architecture for Dynamic Voltage and Frequency Scaling for Multi-core Processor Applications | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-2 | - |
| dc.description.degree | 博士 | - |
| dc.contributor.oralexamcommittee | 賴炎生;陳耀銘;黃顗融;劉邦榮;劉宇晨 | zh_TW |
| dc.contributor.oralexamcommittee | Yen-Shin Lai;Yaow-Ming Chen;Yi-Rong Huang;Pang-Jung Liu;Yu-Chen Liu | en |
| dc.subject.keyword | 動態電壓頻率調控 (DVFS); 數位低壓差線性穩壓器 (DLDO); 全數位鎖相迴路 (AD-PLL); 能源效率; 低功耗; 可拓展化; 每秒百萬指令 (MIPS); 系統單晶片 (SoC) | zh_TW |
| dc.subject.keyword | Dynamic voltage and frequency scaling (DVFS); Digital low-dropout regulator (DLDO); all-digital phase-locked loop (AD-PLL); energy efficient; low power; scalability; million instructions per second (MIPS); system-on-chip (SoC) | en |
| dc.relation.page | 99 | - |
| dc.identifier.doi | 10.6342/NTU202602201 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2026-07-22 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電機工程學系 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電機工程學系 | |
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