請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10187
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Ciao-Ling Peng | en |
dc.contributor.author | 彭巧齡 | zh_TW |
dc.date.accessioned | 2021-05-20T21:08:24Z | - |
dc.date.available | 2016-07-06 | |
dc.date.available | 2021-05-20T21:08:24Z | - |
dc.date.copyright | 2011-07-06 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-05-19 | |
dc.identifier.citation | [1] C. Cao, Y. Ding, and K. K. O, “A 50-GHz Phase-Locked Loop in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1649-1656, August 2007.
[2] C. Lee and S.-I. Liu, “A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2007, pp. 196-197. [3] J. Lee, M. Liu, and H. Wang, “A 75-GHz Phase-Locked Loop Generator in 90-nm CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008. [4] K.-H. Tsai and S.-I. Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2009, pp. 276-277. [5] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, H. C. Luong, “A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18μm CMOS process,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1236-1244, Jun. 2006. [6] W. S.T. Yan, and H. C. Luong, “A 900-MHz CMOS Low-Phase-Noise Voltage-Controlled Ring Oscillator,” IEEE Transactions on Circuits and System, vol. 48, pp. 216-221, February 2001. [7] Y. Ding, K. K. O, “A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 6, June 2007. [8] J. Lee and S. Wu, 'Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology,' Digest of Symposium on VLSI Circuits, pp. 140-143, June 2005. [9] J. Kim, J.-K. Kim, B.-J. Lee, N. Kim, D.-K. Jeong, W. Kim, “A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitter in 0.13-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, April 2006. [10] F.-H. Huang, C.-K. Lin, Y.-C. Wang, and Y.-J. Chan, “A 30 GHz Single-Chip PLL MMIC using 0.5μm Enhanced/Depletion-Mode GaAs pHEMT,” in IEEE Compound Semiconductor Integrated Circuit Symposium Digest, pp. 1-4, 2007. [11] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional hase-frequency detector,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 1019-1022, Aug. 1990. [12] C. S. Vaucher, Architectures for RF Frequency Synthesizers. Boston, MA: Kluwer, 2002. [13] Jri Lee, “High-Speed Circuit Designs for Transmitters in Broadband Data Links,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2349-2358, December 2004. [14] R. C. H. van de Beek and et al., “A 2.5-10-GHz Clock Multiplier Unit With 0.22-ps RMS Jitter in Standard 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, November 2004. [15] H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, “Millimeter-wave CMOS circuit design,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 2, pp. 472-477, Feb. 2005. [16] C. Doan, S. Emami, A. Niknejad, and R. Brodersen, “Millimeter-wave CMOS design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 144-155, Jan. 2005. [17] T. C. Edwards and M. B. Steer, Foundations of Interconnect and Microstrip Design, 3rd ed. New York: Wiley, 2000. [18] B. Kleveland, C. H. Diaz, D. Vook, L. Madden, T. H. Lee, and S. S. Wong, “Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1480-1488, Oct. 2001. [19] M.-J. Chiang, H.-S. Wu, and C.-K. C. Tzuang, “Design of synthetic quasi-TEM transmission line for CMOS compact integrated circuit,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 12, pp. 2512-2520, December 2007. [20] C.-C. Chen and C.-K. C. Tzuang, “Synthetic quasi-TEM meandered transmission lines for compacted microwave integrated circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 6, pp. 1637-1647, Jun. 2004. [21] C.-K. C. Tzuang, C.-H. Chang, H.-S. Wu, S. Wang, S.-X. Lee, C.-C. Chen, C.-Y. Hsu, K.-H. Tsai, and J. Chen, “An X-band CMOS multifunction-chip FMCW radar,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2006, pp. 2011-2014. [22] C.-K. C. Tzuang, H.-H. Wu, H.-S. Wu, and J. Chen, “CMOS active bandpass filter using compacted synthetic quasi-TEM lines at C-band,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4548-4555, December 2006. [23] M.-J. Chiang, H.-S. Wu, and C.-K. C. Tzuang, “Design of CMOS Spiral Inductors for Effective Broadband Shielding,” in 36th EuMC European Microwave Conference Digest, pp. 48-51, Manchester, UK, Sept. 2006. [24] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000. [25] K. J. Wong, A. Rylyakov, and C. K. Yang, “A broadband 44-GHz frequency divider in 90-nm CMOS,” in IEEE Compound Semiconductor Integrated Circuit Symposium Digest, pp. 196-199, 2005. [26] B. Razavi, K. F. Lee, and R.-H. Yan, “A 13.4-GHz CMOS frequency divider,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 1994, pp. 176-177. [27] Jri Lee and B. Razavi, ”A 40 GHz frequency divider in 0.18μm CMOS technology,” in IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2003, pp. 259-262. [28] M. Tiebout, “A 480 μW 2 GHz ultra low power dual-modulus prescaler in 0.25 μm standard CMOS,” in Proceeding of IEEE International Symposium on Circuits and Systems, vol. 5, Switzerland, May 2000, pp. 741-744. [29] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 813-821, June 1999. [30] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high- frequency low-power frequency divider,” IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, July 2004. [31] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 8, pp. 1649-1658, August 2007. [32] Y.-H. Wong, W.-H. Lin, J.-H. Tsai, and T.-W. Huang, “A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, June 2008, pp. 435-438. [33] T.-N. Luo, Y.-J. Emery Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 3, pp. 620-625, March 2008. [34] K. Yamamoto and M. Fujishima, “70GHz CMOS harmonic injection-locked divider,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2006, pp. 2472-2481. [35] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, September 2004. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10187 | - |
dc.description.abstract | 隨著製程的進步,使得射頻積體電路得以趨向高頻發展。由於無線通訊技術在工業、科學以及醫學等三大領域的快速發展與廣泛應用,市場對低成本、低功耗積體電路的需求有日以劇增的趨勢。為了確保毫米波電路能夠正常地運作,常見的方式即是使用較先進的製程來設計電路,但此一方法卻會導致成本的增加進而降低產品競爭力。因此,成本考量與電路性能之間取得平衡是設計者主要的課題。儘管如此,它仍然是一項具有挑戰性的任務。
在本篇論文中,我們藉由改善電路的架構,使得高頻電路如30.4 GHz鎖相迴路,能夠在0.18-μm標準互補式金氧半導體製程中實現,以達到節省成本的目的。由於電路架構的特性,傳統相位頻率偵測器的操作頻率受到明顯地限制,因此首要之務即是使用獨立的相位偵測器及頻率偵測器。除此之外,在壓控振盪器的設計中,我們引用了近橫向電磁傳輸線的技術來實現小面積及高頻的操作。不僅如此,近橫向電磁傳輸線同時還具備了良好的屏蔽能力,讓壓控振盪器本身更加穩定。除了鎖相迴路的架構介紹外,詳細的量測結果將呈現於本論文之後。藉以驗證上述方法之可行性,此鎖相迴路操作於1.8伏之供應電壓,消耗功率為64.8 mW。 | zh_TW |
dc.description.abstract | With the advances of the silicon integrated circuit technologies, radio-frequency IC designs are motivated toward higher frequency. Due to the rapid evolution of the wireless communication in industrial, scientific and medical band, the demands for the low-cost and low-power integrated circuit have been increased. To ensure millimeter-wave circuits and systems work properly, the fabrication technology must be scaled down for high-frequency operations. Unfortunately, there exists a tradeoff between cost and circuit performance. However, it is still a challenging task for the designer to implement millimeter-wave circuits while sustaining lower cost efficiently.
In this thesis, to reduce the cost of the fabricated circuit, a technique of the circuit topology is adopted such that a 30.4 GHz PLL can be realized in standard CMOS technologies. First, independent PD and FD are employed while the conventional PFD structure limits the operating frequency apparently. In addition, the synthetic quasi-TEM transmission line is introduced to the VCO for the small area and higher operating frequency, facilitating circuit implementation in standard 0.18-μm CMOS technologies. Meanwhile, by using the well-designed transmission line, the VCO can be more stable due to good shielding capability. With a standard design procedure of PLL, the experimental results are presented completely for demonstrations. Operated at a 1.8-V supply voltage, the fabricated circuit consumes a dc power of 64.8mW. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T21:08:24Z (GMT). No. of bitstreams: 1 ntu-100-R96943147-1.pdf: 1478809 bytes, checksum: 6465a80b0be503f241d976ae0b36535d (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | Acknowledgement v
Abstract vii Table of Contents xi List of Figures xv List of Tables xix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of this Thesis 3 Chapter 2 Background 7 2.1 Basic Concepts of PLL 7 2.2 Building Blocks of PLL 8 2.2.1 Phase-Frequency Detector & Charge Pump 8 2.2.2 Loop Filter 12 2.2.3 Voltage-Controlled Oscillator 14 2.2.4 Frequency Divider 15 2.3 The Linear Model for PLL 16 2.3.1 Linear Model of PFD & Charge Pump 16 2.3.2 Linear Model of LPF 17 2.3.3 Linear Model of VCO & Frequency Divider 18 2.3.4 Stability Analysis of Phase-Locked Loop 18 2.4 General Design Procedure of Phase-Locked Loop 21 Chapter 3 Design of Synthetic Quasi-TEM Transmission Line for 30GHz PLL 25 3.1 Introduction 25 3.2 Architecture 27 3.3 Circuit Implementation 29 3.3.1 The proposed Topology of VCO 30 3.3.1.1 Microstrip Line & Coplanar Waveguide (CPW) 31 3.3.1.2 Adopted Synthetic Quasi-TEM Transmission Line 32 3.3.2 Injection-Locked Frequency Divider / CML Dividers 36 3.3.3 Phase Detector / Frequency Detector 41 3.4 Simulation Results 45 3.4.1 The Behavior Simulation by Simulink 45 3.4.2 The Propoased VCO 47 3.4.3 The Direct-ILFD 47 3.4.4 The Phase Detector 48 3.4.5 The Locking Process of the PLL 49 Chapter 4 Experimental Results 53 Chapter 5 Conclusion 61 Bibliography 65 | |
dc.language.iso | en | |
dc.title | 以0.18-μm CMOS製程製作之30GHz鎖相迴路設計與實現 | zh_TW |
dc.title | Design and Implementation of 30 GHz Phase-Locked Loop in a 0.18-μm CMOS Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin) | |
dc.subject.keyword | 鎖相迴路,近橫向電磁傳輸線,毫米波, | zh_TW |
dc.subject.keyword | phase-locked loop,synthetic quasi-TEM transmission line,millimeter-wave, | en |
dc.relation.page | 69 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2011-05-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-100-1.pdf | 1.44 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。